A DC Chopper Topology to Mitigate Commutation Failure of Line Commutated Converter Based High Voltage Direct Current Transmission

To reduce the probability of commutation failure(CF)of a line commutated converter based high-voltage direct current(LCC-HVDC)transmission,a DC chopper topology composed of power consumption sub-modules based on thyristor full-bridge module(TFB-PCSM)is proposed.Firstly,the mechanism of the proposed topology to mitigate CF is analyzed,and the working modes of TFB-PCSM in different operation states are introduced.Secondly,the coordinated control strategy between the proposed DC chopper and LCC-HVDC is designed,and the voltage-current stresses of the TFB-PCSMs are investigated.Finally,the ability to mitigate the CF issues and the fault recovery performance of LCC-HVDC system are studied in PSCAD/EMTDC.The results show that the probability of CF of LCC-HVDC is significantly reduced,and the performances of fault recovery are effectively improved by the proposed DC chopper.

Traveling Wave Characteristics Based Pilot Protection Scheme for Hybrid Cascaded HVDC Transmission Line

The hybrid cascaded high-voltage direct current(HVDC)transmission system has various operation modes,and some operation modes have sharply increasing requirements for protection rapidity,while the traditional pilot differential protection(PDP)has poor rapidity,and even refuses to operate when faults occur on the DC line.Therefore,a novel pilot protection scheme based on traveling wave characteristics is proposed.First,the adaptability of the traditional PDP applied in engineering is analyzed for different operation modes.Then,the expressions of the forward traveling wave(FTW)and backward traveling wave(BTW)on the rectifier side and the inverter side are derived for different fault locations.From the theoretical derivation,the difference between the BTW and FTW on the rectifier side is less than zero,and the same is true on the inverter side.However,in the event of an external fault of DC line,the difference between the BTW and FTW at nearfault terminal protection installation point is greater than zero.Therefore,by summing over the product of the difference between BTW and FTW of the rectifier side and that of the inverter side,the fault identification criterion is constructed.The simulation results show that the proposed pilot protection scheme can quickly and reliably identify the short-circuit faults of DC line in different operation modes.

Overview of development, design, testing and application of compact gas-insulated DC systems up to ±550 kV

The development of high-voltage direct current gas-insulated switchgear assemblies(DC GIS)of rated voltages up to±550 kV has been completed.DC GIS provide a compact technical solution with a high functional density,optimized for projects with limited space as in offshore HVDC converter platforms,onshore HVDC converter stations and transition stations between different transmission media.Up to now,no standards for testing of gas-insulated DC systems are available,although pre-standardization work is in progress within CIGRE.Some tests can be performed as required in AC GIS standards.Special aspects of DC voltage stress,like the electric field distribution of insulators influenced by the accumulation of electrical charge carriers and the operation-related inhomogeneous temperature distribution,must be considered by additional electric and thermoelectric tests.For DC GIS,the experience of long-term performance is limited today.Although ageing is expected to be of lower importance,tests are recommended.This contribution summarizes the physical and technical background to design and develop compact DC switchgear assemblies using gas-insulated technology.It explains the developed modules of the substation and gives an overview of the performed tests.Furthermore,it provides an insight in the on-going standardization activities and describes applications in converter and transition stations,showing its space-saving characteristics.

Single-end Protection Scheme Based on Transient Power Waveshape for Hybrid HVDC Transmission Lines

The recent in-depth development of hybrid highvoltage direct current(HVDC) transmission systems poses looming adaptability challenges to protection. The various and disparate direct current(DC) transmission topologies can profoundly affect the operating characteristics of DC transmission networks, which result in the lack of performance of conventional DC protection schemes in such topologies. This significantly limits the application of hybrid HVDC technologies. This paper proposes a single-end protection scheme based on the transient power waveshape for fast and sensitive detection and classification of different types of DC faults in hybrid HVDC transmission lines. The fault characteristics and their causes under different fault conditions are analyzed in detail with a pre-introduced linearized transient model of a hybrid HVDC transmission system, demonstrating that the formation of the fluctuation characteristics of local measurements is mainly determined by the buffering and absorption effects of lumped-parameter reactors on transient traveling-wave(TW) energy. Simulation results verify the sensitivity, rapidity, reliability, and anti-interference ability of the proposed scheme when applied to hybrid HVDC transmission lines. Furthermore, it is confirmed that the proposed scheme is adaptable to symmetric voltage-sourced converter(VSC) and conventional line-commutated converter(LCC) based HVDC transmission lines.

Joint Limiting Control Strategy Based on Virtual Impedance Shaping for Suppressing DC Fault Current and Arm Current in MMC-HVDC Systems

This paper proposes a joint limiting control strategy for suppressing DC fault current and arm current in modular multilevel converter-based high-voltage direct current(MMC-HVDC) systems, which includes two target-oriented current limiting controls. To limit the DC fault current in the early fault stage, an equivalent modular multilevel converter(MMC) impedance is obtained, and its high-frequency part is reshaped by introducing virtual impedance, which is realized by adjusting the inserted submodules adaptively. Following the analysis of MMC control characteristics, the arm current limiting strategy is investigated, with results showing that the inner-loop control has significant effects on arm current and that a simple low-pass filter can reduce the arm current in the fault period. Finally, by combining the virtual impedance shaping and innerloop control, the fault currents of DC lines and MMC arms can be suppressed simultaneously, which can not only alleviate the interrupting pressure of the DC circuit breaker, but also prevent the MMC from being blocked by the arm overcurrent. Theoretical analysis conclusions and the proposed strategy are verified offline by a digital time-domain simulation on Power Systems Computer Aided Design/Electromagnetic Transients including DC platform, and experiment on a real-time digital simulator platform.

Phasor Analytical Model of Non-isolated DC/DC Converter Based on Modular Multilevel Converter for DC Transmission Grids

Non-isolated DC/DC converter based on modular multilevel converter(MMC)technology is expected to play an important role in future DC transmission grids.This paper presents a phasor analytical model for this new family of converters which is suitable for a range of studies like DC grid power flow or DC/DC parametric design.The 30th-order phasor model is derived in 3 coordinate frames:zero sequence(DC),fundamental frequency(dq),and double frequency(d2q2).The second-harmonic current suppression control is included as an option.Additionally,an estimation of the required control signals is presented,and a closed-loop model is developed which facilitates direct calculation of all variables and fast parametric studies.The accuracy of the proposed models is verified against a detailed PSCAD model for a wide range of parameters.The studies illustrate the importance of the second-harmonic components on the model accuracy.Finally,the impact of the converter parameters on the performance is studied,and a basic eigenvalue stability analysis is given.

Thyristor-inserted MMC Sub-module Topology with DC Fault Blocking Capability

Modular multilevel converter(MMC)is increasingly being applied to high voltage direct current(HVDC)systems.However,dc short circuit situations restrain the application of a conventional half bridge MMC system.In this paper,a new sub-module topology with inserted thyristor can help the MMC system clear a dc side fault.Working states and devices voltage stress of the proposed topology are analyzed and the conduction loss comparison between the proposed topology with several existing topologies with dc fault blocking capability is carried out.Results show the proposed topology is superior to other topologies in terms of conduction loss while using the same voltage rating devices.Besides,compared with traditional half bridge topology,only thyristors and diodes are added in the proposed topology.Therefore,cost of the proposed topology can be lower than conventional hybrid MMC sub-modules.At last,the fault blocking capability of the proposed topology is verified in the simulation.

Improved Identification Method and Fault Current Limiting Strategy for Commutation Failure in LCC-HVDC

Line-commutated converter based high-voltage direct-current(LCC-HVDC)transmission systems are prone to subsequent commutation failure(SCF),which consequently leads to the forced blocking of HVDC links,affecting the operation of the power system.An accurate commutation failure(CF)identification is fairly vital to the prevention of SCF.However,the existing CF identification methods cause CF misjudge or detection lag,which can limit the effect of SCF mitigation strategy.In addition,earlier approaches to suppress SCF do not clarify the key factor that determines the evolution of extinction angle during system recovery and neglect the influence.Hence,this paper firstly analyzes the normal commutation process and CF feature based on the evolution topology of converter valve conduction in detail.Secondly,the energy in the leakage inductance of converter transformer is presented to characterize the commutation state of the valves.Then a CF identification method is proposed utilizing the leakage inductance energy.Thirdly,taking the key variable which is crucial to the tendency of extinction angle during the recovery process into account,a fault current limiting strategy for SCF mitigation is put forward.Compared with the original methods,the proposed methods have a better performance in CF identification and mitigation in terms of detection accuracy and mitigation effect.Finally,case study on PSCAD/EMTDC validates the proposed methods.

Continuous Commutation Failure Suppression Method Based on Self-adaptive Auto-disturbance Rejection Proportional-integral Controller for HVDC Transmission System

Once an asymmetrical fault occurs on the AC side of the receiving-end of a high-voltage direct current(HVDC)transmission system,the current reference will be affected by the control regulation on the DC inverter side and the commutation voltage asymmetry.In this case,the advance firing angle will fluctuate periodically,causing security threats to the system.If the fault cannot be cleared in time,the effect may be even more serious.However,the traditional proportional-integral(PI)controller cannot effectively suppress the periodic components in the input error signal,which is an important cause of continuous commutation failure.Thus,the system requires more time to recover from the fault.Motivated by this,a selfadaptive auto-disturbance rejection PI controller is proposed in this study.The controller has the advantages of fast response speed and strong anti-interference ability of the auto-disturbance rejection controller.On one hand,it can automatically adjust PI,and the parameters can maintain the system’s adaptive ability.On the other hand,the discretization process satisfies the computer simulation requirements.By applying the proposed controller to a system under constant current control and extinction angle control,the dynamic response speed can be improved and the robust performance of the system can be ensured when dealing with a wide range of perturbations.Finally,simulation results show that the proposed algorithm can effectively suppress the continuous commutation failure of DC transmission systems.

Low Impedance Fault Identification and Classification Based on Boltzmann Machine Learning for HVDC Transmission Systems

Identification and classification of DC faults are considered as fundamentals of DC grid protection.A sudden rise of DC fault current must be identified and classified to immediately operate the corresponding interrupting mechanism.In this paper,the Boltzmann machine learning(BML)approach is proposed for identification and classification of DC faults using travelling waves generated at fault point in voltage source converter based high-voltage direct current(VSC-HVDC)transmission system.An unsupervised way of feature extraction is performed on the frequency spectrum of the travelling waves.Binomial class logistic regression(BCLR)classifies the HVDC transmission system into faulty and healthy states.The proposed technique reduces the time for fault identification and classification because of reduced tagged data with few characteristics.Therefore,the faults near or at converter stations are readily identified and classified.The performance of the proposed technique is assessed via simulations developed in MATLAB/Simulink and tested for pre-fault and post-fault data both at VSC1 and VSC2,respectively.Moreover,the proposed technique is supported by analyzing the root mean square error to show practicality and realization with reduced computations.