Amplitude quantization is one of the main sources of spurious noise frequencies in Direct Digital Frequency Synthesizers (DDFSs), which affect their application to many wireless telecommu- nication systems. In this pa...Amplitude quantization is one of the main sources of spurious noise frequencies in Direct Digital Frequency Synthesizers (DDFSs), which affect their application to many wireless telecommu- nication systems. In this paper, two different kinds of spurious signals due to amplitude quantization in DDFSs are exactly formulated in the time domain and detailedly compared in the frequency do- main, and the effects of the DDFS parameter variations on the spurious performance are thoroughly studied. Then the spectral properties and power levels of the amplitude-quantization spurs in the absence of phase-accumulator truncation are emphatically analyzed by waveform estimation and computer simulation, and several important conclusions are derived which can provide theoretical support for parameter choice and spurious performance evaluation in the application of DDFSs.展开更多
This paper presents a high speed ROM-less direct digital frequency synthesizer （DDFS） which has a phase resolution of 32 bits and a magnitude resolution of 10 bits. A 10-bit nonlinear segmented DAC is used in place ...This paper presents a high speed ROM-less direct digital frequency synthesizer （DDFS） which has a phase resolution of 32 bits and a magnitude resolution of 10 bits. A 10-bit nonlinear segmented DAC is used in place of the ROM look-up table for phase-to-sine amplitude conversion and the linear DAC in a conventional DDFS. The design procedure for implementing the nonlinear DAC is presented. To ensure high speed, current mode logic （CML） is used. The chip is implemented in Chartered 0.35μm COMS technology with active area of 2.0 × 2.5 mm^2 and total power consumption of 400 mW at a single 3.3 V supply voltage. The maximum operating frequency is 850 MHz at room temperature and 1.0 GHz at 0℃.展开更多
This paper presents a novel direct digital frequency synthesizer （DDFS） architecture based on nonlinear DAC coarse quantization and the ROM-based piecewise approximation method, which has the advantages of high spee...This paper presents a novel direct digital frequency synthesizer （DDFS） architecture based on nonlinear DAC coarse quantization and the ROM-based piecewise approximation method, which has the advantages of high speed, low power and low hardware resources. By subdividing the sinusoid into a collection of phase segments, the same initial value of each segment is realized by a nonlinear DAC. The ROM is decomposed with a coarse ROM and fine ROM using the piecewise approximation method. Then, the coarse ROM stores the offsets between the initial value of the common segment and the initial value of each line in the same segment. Meanwhile, the fine ROM stores the differences between the line values and the initial value of each line. A ROM compression ratio of 32 can be achieved in the case of 11 bit phase and 9 bit amplitude. Based on the above method, a prototype chip was fabricated using 1.4 #m GaAs HBT technology. The measurement shows an average spurious-free dynamic range （SFDR） of 45 dBc, with the worst SFDR only 40.07 dBc at a 4.0 GHz clock. The chip area is 4.6 × 3.7 mm2 and it consumes 7 W from a --4.9 V power supply.展开更多
This paper presents a direct digital frequency synthesizer （DDFS） for high speed application based on multi-channel structure. This DDFS has phase resolution of 32 bits and magnitude resolution of 12 bits. In order ...This paper presents a direct digital frequency synthesizer （DDFS） for high speed application based on multi-channel structure. This DDFS has phase resolution of 32 bits and magnitude resolution of 12 bits. In order to ensure the high speed and high resolution at the same time, the multi-channel sampling technique is used and a 12 bits linear digital-to-analog converter is implemented. The chip is fabricated in TSMC 130 nm CMOS technology with active area of 0.89 x 0.98 mm2 and total power consumption of 300 mW at a single 1.2 V supply voltage. The maximum operating speed is up to 2.0 GHz at room temperature.展开更多
This paper presents a detailed description of a high-performance direct digital frequency synthesizer （DDFS） using optimized quarter ROMs. To improve the working frequency and spectral purity, an original quarter RO...This paper presents a detailed description of a high-performance direct digital frequency synthesizer （DDFS） using optimized quarter ROMs. To improve the working frequency and spectral purity, an original quarter ROMs structure in 0.13 μm CMOS is brought forward and implemented. The working frequency is increased by 40% compared with Yuan Ling＇s methodIll of implementing a segmented DAC based DDFS. It has been implemented in 0.13 μm CMOS technology. The DDFS has a resolution of 10 bits with a measured SFDR 54 dBc. Its maximum operating frequency is 1.2 GHz by using six pipelining stages. Analytical investigation of improving spectral performances by using dual-slope approximation and pipeline is also presented.展开更多
介绍了直接数字波形合成(direct digital waveform synthesizer,DDWS)的误差来源,分析了DDWS结构中其数模转换器(DAC)信号重构机理,比较研究了DAC信号重构误差对输出信号脉冲压缩结果的影响。提出了一种针对DAC带来的信号辛格函数调制...介绍了直接数字波形合成(direct digital waveform synthesizer,DDWS)的误差来源,分析了DDWS结构中其数模转换器(DAC)信号重构机理,比较研究了DAC信号重构误差对输出信号脉冲压缩结果的影响。提出了一种针对DAC带来的信号辛格函数调制误差的数字化补偿算法,对中频30 MHz,带宽分别为40 MHz和20 MHz的超宽带低中频线性调频信号进行了实际补偿。实验结果表明该算法简单方便,能有效补偿DAC带来的波形调制误差。展开更多
基金Supported by National High-Technology Research and Development Plan of China (Grant No.2006AA01Z452)
文摘Amplitude quantization is one of the main sources of spurious noise frequencies in Direct Digital Frequency Synthesizers (DDFSs), which affect their application to many wireless telecommu- nication systems. In this paper, two different kinds of spurious signals due to amplitude quantization in DDFSs are exactly formulated in the time domain and detailedly compared in the frequency do- main, and the effects of the DDFS parameter variations on the spurious performance are thoroughly studied. Then the spectral properties and power levels of the amplitude-quantization spurs in the absence of phase-accumulator truncation are emphatically analyzed by waveform estimation and computer simulation, and several important conclusions are derived which can provide theoretical support for parameter choice and spurious performance evaluation in the application of DDFSs.
文摘This paper presents a high speed ROM-less direct digital frequency synthesizer （DDFS） which has a phase resolution of 32 bits and a magnitude resolution of 10 bits. A 10-bit nonlinear segmented DAC is used in place of the ROM look-up table for phase-to-sine amplitude conversion and the linear DAC in a conventional DDFS. The design procedure for implementing the nonlinear DAC is presented. To ensure high speed, current mode logic （CML） is used. The chip is implemented in Chartered 0.35μm COMS technology with active area of 2.0 × 2.5 mm^2 and total power consumption of 400 mW at a single 3.3 V supply voltage. The maximum operating frequency is 850 MHz at room temperature and 1.0 GHz at 0℃.
基金supported by the National Basic Research Program of China(No.2010CB327505)
文摘This paper presents a novel direct digital frequency synthesizer （DDFS） architecture based on nonlinear DAC coarse quantization and the ROM-based piecewise approximation method, which has the advantages of high speed, low power and low hardware resources. By subdividing the sinusoid into a collection of phase segments, the same initial value of each segment is realized by a nonlinear DAC. The ROM is decomposed with a coarse ROM and fine ROM using the piecewise approximation method. Then, the coarse ROM stores the offsets between the initial value of the common segment and the initial value of each line in the same segment. Meanwhile, the fine ROM stores the differences between the line values and the initial value of each line. A ROM compression ratio of 32 can be achieved in the case of 11 bit phase and 9 bit amplitude. Based on the above method, a prototype chip was fabricated using 1.4 #m GaAs HBT technology. The measurement shows an average spurious-free dynamic range （SFDR） of 45 dBc, with the worst SFDR only 40.07 dBc at a 4.0 GHz clock. The chip area is 4.6 × 3.7 mm2 and it consumes 7 W from a --4.9 V power supply.
文摘This paper presents a direct digital frequency synthesizer （DDFS） for high speed application based on multi-channel structure. This DDFS has phase resolution of 32 bits and magnitude resolution of 12 bits. In order to ensure the high speed and high resolution at the same time, the multi-channel sampling technique is used and a 12 bits linear digital-to-analog converter is implemented. The chip is fabricated in TSMC 130 nm CMOS technology with active area of 0.89 x 0.98 mm2 and total power consumption of 300 mW at a single 1.2 V supply voltage. The maximum operating speed is up to 2.0 GHz at room temperature.
文摘This paper presents a detailed description of a high-performance direct digital frequency synthesizer （DDFS） using optimized quarter ROMs. To improve the working frequency and spectral purity, an original quarter ROMs structure in 0.13 μm CMOS is brought forward and implemented. The working frequency is increased by 40% compared with Yuan Ling＇s methodIll of implementing a segmented DAC based DDFS. It has been implemented in 0.13 μm CMOS technology. The DDFS has a resolution of 10 bits with a measured SFDR 54 dBc. Its maximum operating frequency is 1.2 GHz by using six pipelining stages. Analytical investigation of improving spectral performances by using dual-slope approximation and pipeline is also presented.
