A jamming signal such as single and multiple Continuous-Wave (CW and MCW) interferences have been shown to have severe effects on the quality of the received signal in wireless communication. This paper presents an ap...A jamming signal such as single and multiple Continuous-Wave (CW and MCW) interferences have been shown to have severe effects on the quality of the received signal in wireless communication. This paper presents an approach of a low-complexity algorithm that compares the performances of using Adaptive Notch Filter (ANF) direct and lattice forms structures based on second-order Infinite Impulse Response (IIR) Notch Filter (NF) for the detection and mitigation of CW and MCW interferences in QPSK communication systems. The approach method consists of two ANFs, adaptive IIR NF and adaptive IIR NF . The present algorithm can estimate and mitigate each CWI and computer their power in Time-Domain (TD). In results for performance comparison, the lattice IIR NF structure outperforms the direct IIR NF structure for detection and removal jamming and has a better Bit Error Ratio (BER). Furthermore, compared with the case of full suppression (), both cases (direct and lattice form) work better for low and high-power jammers. Also, compared to the case without an IIR NF, the presented algorithm can detect and mitigate, track hopping frequency interference, and improve BER performance.展开更多
Improvement of digital FIR filter is vital in the field of Digital Signal Processing in order to reduce the area, delay and power. Multiplication and Accumulation (MAC) unit of Finite Impulse Response (FIR) filte...Improvement of digital FIR filter is vital in the field of Digital Signal Processing in order to reduce the area, delay and power. Multiplication and Accumulation (MAC) unit of Finite Impulse Response (FIR) filter has been designed using efficient multiplier and adder circuits for optimized APT (Area,Power and Timing) product. In this paper, the design of direct form FIR filter with efficient MAC unit has been presented. Initially, full adder and half adder structures are shrunk down by reducing number of gates. These compact full adder and half adder structures are incorporated into Wallace Multiplier and Improved Carry-Save Adder. The proposed 16-bit Carry-Save Adder has been improved by splitting into four parallel phases. Consequently the delay of enhanced Carry- Save Adder is reduced. Generation of carry output is performed using number of OR gates in a sequential manner. All these enhanced architectures are incorporated into the Digital FIR Filter to reduce the area, delay and power utilization.展开更多
文摘A jamming signal such as single and multiple Continuous-Wave (CW and MCW) interferences have been shown to have severe effects on the quality of the received signal in wireless communication. This paper presents an approach of a low-complexity algorithm that compares the performances of using Adaptive Notch Filter (ANF) direct and lattice forms structures based on second-order Infinite Impulse Response (IIR) Notch Filter (NF) for the detection and mitigation of CW and MCW interferences in QPSK communication systems. The approach method consists of two ANFs, adaptive IIR NF and adaptive IIR NF . The present algorithm can estimate and mitigate each CWI and computer their power in Time-Domain (TD). In results for performance comparison, the lattice IIR NF structure outperforms the direct IIR NF structure for detection and removal jamming and has a better Bit Error Ratio (BER). Furthermore, compared with the case of full suppression (), both cases (direct and lattice form) work better for low and high-power jammers. Also, compared to the case without an IIR NF, the presented algorithm can detect and mitigate, track hopping frequency interference, and improve BER performance.
文摘Improvement of digital FIR filter is vital in the field of Digital Signal Processing in order to reduce the area, delay and power. Multiplication and Accumulation (MAC) unit of Finite Impulse Response (FIR) filter has been designed using efficient multiplier and adder circuits for optimized APT (Area,Power and Timing) product. In this paper, the design of direct form FIR filter with efficient MAC unit has been presented. Initially, full adder and half adder structures are shrunk down by reducing number of gates. These compact full adder and half adder structures are incorporated into Wallace Multiplier and Improved Carry-Save Adder. The proposed 16-bit Carry-Save Adder has been improved by splitting into four parallel phases. Consequently the delay of enhanced Carry- Save Adder is reduced. Generation of carry output is performed using number of OR gates in a sequential manner. All these enhanced architectures are incorporated into the Digital FIR Filter to reduce the area, delay and power utilization.
