An increase in the cache capacity is usually accompanied by a decrease in access speed.To balance the capacity and performance of caches,this paper proposes an instruction cache(ICache)architecture based on divide-by-...An increase in the cache capacity is usually accompanied by a decrease in access speed.To balance the capacity and performance of caches,this paper proposes an instruction cache(ICache)architecture based on divide-by-2 memory banks(D2MB-ICache).The control circuit and memory banks of D2MB-ICache work at the central processing unit(CPU)frequency and the divide-by-2 CPU frequency,respectively,so that the capacity of D2MB-ICache can be expanded without lowering its frequency.For sequential access,D2MB-ICache can output the required instruction from memory banks per CPU cycle by dividing the memory banks with a partition mechanism and employing an inversed clock technique.For non-sequential access,D2MB-ICache will fetch certain jump instructions one or two more times,so that it can catch the jump of the request address in time and send the correct instruction to the pipeline.Experimental results show that,compared with conventional ICache,D2MB-ICaches with the same and double capacities show a maximum frequency increase by an average of 14.6%and 6.8%,and a performance improvement by an average of 10.3%and 3.8%,respectively.Moreover,energy efficiency of 64-kB D2MB-ICache is improved by 24.3%.展开更多
An integrated low power CMOS VCO and its divide by 2 dividers for WLAN transceivers are presented.The VCO is based on on chip symmetrical spiral inductor and differential diode and the divide by 2 dividers are b...An integrated low power CMOS VCO and its divide by 2 dividers for WLAN transceivers are presented.The VCO is based on on chip symmetrical spiral inductor and differential diode and the divide by 2 dividers are based on the ILFD technique.Due to differential LC tanks and ILFD techniques,power consumption is low.The circuit is implemented in a 0 18μm CMOS process.Measurements show the proposed circuit could produce 3 6/1 8GHz dual band LO signals with a wide tuning range and low phase noise.1 8GHz LO signals are quadrature.It consumes 5mA at V DD =1 5V.The size of die area is only 1 0mm×1 0mm.展开更多
基金the Postgraduate Research Innovation Program of Jiangsu Province under Grant No.KYCX20_1936the Fundamental Research Funds for the Central Universities under Grant No.JUSRP51510the Key Research and Development Program of Jiangsu under Grant No.BE2019003-2.
文摘An increase in the cache capacity is usually accompanied by a decrease in access speed.To balance the capacity and performance of caches,this paper proposes an instruction cache(ICache)architecture based on divide-by-2 memory banks(D2MB-ICache).The control circuit and memory banks of D2MB-ICache work at the central processing unit(CPU)frequency and the divide-by-2 CPU frequency,respectively,so that the capacity of D2MB-ICache can be expanded without lowering its frequency.For sequential access,D2MB-ICache can output the required instruction from memory banks per CPU cycle by dividing the memory banks with a partition mechanism and employing an inversed clock technique.For non-sequential access,D2MB-ICache will fetch certain jump instructions one or two more times,so that it can catch the jump of the request address in time and send the correct instruction to the pipeline.Experimental results show that,compared with conventional ICache,D2MB-ICaches with the same and double capacities show a maximum frequency increase by an average of 14.6%and 6.8%,and a performance improvement by an average of 10.3%and 3.8%,respectively.Moreover,energy efficiency of 64-kB D2MB-ICache is improved by 24.3%.
文摘An integrated low power CMOS VCO and its divide by 2 dividers for WLAN transceivers are presented.The VCO is based on on chip symmetrical spiral inductor and differential diode and the divide by 2 dividers are based on the ILFD technique.Due to differential LC tanks and ILFD techniques,power consumption is low.The circuit is implemented in a 0 18μm CMOS process.Measurements show the proposed circuit could produce 3 6/1 8GHz dual band LO signals with a wide tuning range and low phase noise.1 8GHz LO signals are quadrature.It consumes 5mA at V DD =1 5V.The size of die area is only 1 0mm×1 0mm.
