Rational architecture design of yolk/double-shells Si-based anode material with double buffering carbon layers for high performance lithium-ion battery

Among the many strategies to fabricate the silicon/carbon composite,yolk/double-shells structure can be regarded as an effective strategy to overcome the intrinsic defects of Si-based anode materials for Li-ion batteries(LIBs).Hereon,a facile and inexpensive technology to prepare silicon/carbon composite with yolk/double-shells structure is proposed,in which the double buffering carbon shells are fabricated.The silicon/carbon nanoparticles with core-shell structure are encapsulated by SiO_(2)and external carbon layer,and it shows the yolk/double-shells structure via etching the SiO_(2)sacrificial layer.The multiply shells structure not only significantly improves the electrical conductivity of composite,but also effectively prevents the exposure of Si particles from the electrolyte composition.Meanwhile,the yolk/double-shells structure can provide enough space to accommodate the volume change of the electrode during charge/discharge process and avoid the pulverization of Si particles.Moreover,the as-prepared YDS-Si/C shows excellent performance as anode of LIBs,the reversible capacity is as high as 1066 mA h g^(-1) at the current density of 0.5 A g^(-1) after 200 cycles.At the same time,the YDS-Si/C has high capacity retention and good cyclic stability.Therefore,the unique architecture design of yolk/double-shells for Si/C composite provides an instructive exploration for the development of next generation anode materials of LIBs with high electrochemical performances and structural stability.

A Non-Stop Double Buffering Mechanism for Dataflow Architecture

Double buffering is an effective mechanism to hide the latency of data transfers between on-chip and off-chip memory. However, in dataflow architecture, the swapping of two buffers during the execution of many tiles decreases the performance because of repetitive filling and draining of the dataflow accelerator. In this work, we propose a non-stop double buffering mechanism for dataflow architecture. The proposed non-stop mechanism assigns tiles to the processing element array without stopping the execution of processing elements through optimizing control logic in dataflow architecture. Moreover, we propose a work-flow program to cooperate with the non-stop double buffering mechanism. After optimizations both on control logic and on work-flow program, the filling and draining of the array needs to be done only once across the execution of all tiles belonging to the same dataflow graph. Experimental results show that the proposed double buffering mechanism for dataftow architecture achieves a 16.2% average efficiency improvement over that without the optimization.

Increase of brightness and transmission efficiency in fiat panel display through serial synchronous scanning mode with double buffers

This paper presents a serial synchronous scanning mode in fiat panel display （FPD） by adding a latch buffer between the serializer and the driving buffer. Comparing with conventional techniques, the proposed structure can efficiently reduce the brightness loss and improve the transmission performance. Theoretical analysis and experimental results show that the ratio between the lightest weight display time and the relative transmission time is a tradeoff between brightness loss and transmission efficiency.

Power Control and Data Acquisition System for High Power Microwave Test Bench

The 6 MW/4.6 GHz lower hybrid current drive （LHCD） system will be set up on the experimental advanced superconducting tokamak （EAST） for achieving a steady-state op- eration. The high power and continuous wave （CW） mode microwave test bench operating at 250 kW/4.6 GHz has already been finished, which can be used to simulate different kinds of high power microwave environments to test microwave components and units for the new LHCD sys- tem. The power control and data acquisition system on the test bench composed of power control, high reflected power protection and data acquisition function is described here in detail. Long- term operation of the test bench showed that the power control and data acquisition system is very stable and reliable.

Growth of High-Quality InP-on-GaAs Quasi-Substrates Using Double Low-Temperature Buffers and Strained Layer Surperlattices by MOCVD

We investigate the growth of InP-on-GaAs combined with the advantages of double low-temperature （LT） buffers and strained layer surperlattices （SLSs）. It is found that LT-InP/LT-GaAs double LT buffers are more effective for strain accommodation than a LT-InP single buffer in InP-on-GaAs. On the other hand, there is an optimal thickness for LT-GaAs for a given thickness of the LT-InP layer,at which the double LT buffers can reach the best state for strain ad- justment. Furthermore,the position of insertion of SLSs should be carefully designed because the distance above the InP/ buffer interface plays an important role in threading dislocation interactions for dislocation reduction. As a result, the density of threading dislocations in the InP epilayer is markedly reduced. X-ray diffraction measurements show that the full width at half maximum of the ω/2θ rocking curve for the 2μm-thick InP epilayer is less than 200.

Promising Cd-free double buffer layer in CZTSSe thin film solar cells

Zn(O,S)film is widely used as a Cd-free buffer layer for kesterite thin film solar cells due to its low-cost and eco-friendly characteristics.However,the low carrier concentration and conductivity of Zn(O,S)will deteriorate the device performance.In this work,an additional buffer layer of In2S3 is introduced to modify the properties of the Zn(O,S)layer as well as the CZTSSe layer via a post-annealing treatment.The carrier concentrations of both the Zn(O,S)and CZTSSe layers are increased,which facilitates the carrier separation and increases the open circuit voltage(VOC).It is also found that ammonia etching treatment can remove the contamination and reduce the interface defects,and there is an increase of the surface roughness of the In2S3 layer,which works as an antireflection layer.Consequently,the efficiency of the CZTSSe solar cells is improved by 24%after the annealing and etching treatments.Simulation and experimental results show that a large band offset of the In2S3 layer and defect energy levels in the Zn(O,S)layer are the main properties limiting the fill factor and efficiency of these CZTSSe devices.This study affords a new perspective for the carrier concentration enhancement of the absorber and buffer layers by In-doping,and it also indicates that In2S3/Zn(O,S)is a promising Cd-free hybrid buffer layer for high-efficiency kesterite solar cells.