Investigation and statistical modeling of InAs-based double gate tunnel FETs for RF performance enhancement

In this paper,RF performance analysis of In As-based double gate（DG）tunnel field effect transistors（TFETs）is investigated in both qualitative and quantitative fashion.This investigation is carried out by varying the geometrical and doping parameters of TFETs to extract various RF parameters,unity gain cut-off frequency（f_t）,maximum oscillation frequency（f_（max））,intrinsic gain and admittance（Y）parameters.An asymmetric gate oxide is introduced in the gate-drain overlap and compared with that of DG TFETs.Higher ON-current（ION）of about 0.2 mA and less leakage current（IOFF）of 29 f A is achieved for DG TFET with gate-drain overlap.Due to increase in transconductance（g_m）,higher ft and intrinsic gain is attained for DG TFET with gate-drain overlap.Higher f_（max） of 985 GHz is obtained for drain doping of 5×10^（17）cm^（-3） because of the reduced gate-drain capacitance（C_（gd））with DG TFET with gate-drain overlap.In terms of Y-parameters,gate oxide thickness variation offers better performance due to the reduced values of Cgd.A second order numerical polynomial model is generated for all the RF responses as a function of geometrical and doping parameters.The simulation results are compared with this numerical model where the predicted values match with the simulated values.

A 14-bit 40-MHz analog front end for CCD application

A 14-bit,40-MHz analog front end（AFE） for CCD scanners is analyzed and designed.The proposed system incorporates a digitally controlled wideband variable gain amplifier（VGA） with nearly 42 dB gain range,a correlated double sampler（CDS） with programmable gain functionality,a 14-bit analog-to-digital converter and a programmable timing core.To achieve the maximum dynamic range,the VGA proposed here can linearly amplify the input signal in a gain range from-1.08 to 41.06 dB in 6.02 dB step with a constant bandwidth.A novel CDS takes image information out of noise,and further amplifies the signal accurately in a gain range from 0 to 18 dB in0.035 dB step.A 14-bit ADC is adopted to quantify the analog signal with optimization in power and linearity.An internal timing core can provide flexible timing for CCD arrays,CDS and ADC.The proposed AFE was fabricated in SMIC 0.18 μm CMOS process.The whole circuit occupied an active area of 2.8×4.8 mm^2 and consumed360 mW.When the frequency of input signal is 6.069 MHz,and the sampling frequency is 40 MHz,the signal to noise and distortion（SNDR） is 70.3 dB,the effective number of bits is 11.39 bit.