Gigahertz frequency hopping in an optical phase-locked loop for Raman lasers

Raman lasers are essential in atomic physics,and the development of portable devices has posed requirements for time-division multiplexing of Raman lasers.We demonstrate an innovative gigahertz frequency hopping approach of a slave Raman laser within an optical phase-locked loop(OPLL),which finds practical application in an atomic gravimeter,where the OPLL frequently switches between near-resonance lasers and significantly detuned Raman lasers.The method merges the advantages of rapid and extensive frequency hopping with the OPLL’s inherent low phase noise,and exhibits a versatile range of applications in compact laser systems,promising advancements in portable instruments.

EFFECTIVE DOUBLE LOOP CONTROL FOR A SQUARE WAVE BRUSHLESS DC MOTOR

A new type of brushless DC motor has been developed by using a square wave rare earth permanent magnet synchronous motor with its double loop control circuit. The double loop control scheme of the drive system yields a combination of desired characteristics including simplified control structure, small ripple torque, high speed accuracy, wide operating speed range, and fast dynamic response. Experimental results confirm excellent characteristics of the motor.

11.6-GHz 0.18-μm monolithic CMOS phase-locked loop

A design of a ll. 6-GHz phase-locked loop （PLL） fabricated in 49-GHz 0. 18-μm CMOS （complementary metal-oxide-semiconductor transistor） technology is described. An analog multiplier phase detector （PD）, a one-pole passive low pass filter and a three-stage ring oscillator with variable negativeresistance loads build up the monolithic phase-locked loop. The measured rms jitter of output signal via onwafer testing is 2. 2 ps under the stimulation of 2^31 - 1 bit-long pseudo random bit sequence （PRBS） at the bit rate of 11.6 GHz. And the tracking range is 250 MHz. The phase noise in the locked condition is measured to be - 107 dBc/Hz at 10 MHz offset, and that of the ring VCO at the central frequency is -99 dBc/Hz at 10 MHz offset. The circuit area of the proposed PLL is only 0. 47mm×0.72mm and the direct current （DC） power dissipation is 164 mW under a 1.8-V supply.

Endoscopic treatment of efferent loop syndrome with insertion of double pigtail stent

Efferent loop syndrome is a very rare postgastrectomy syndrome that can occur following Billroth-Ⅱor Rouxen-Y reconstruction.The most common loop syndrome after gastric surgery is afferent loop syndrome;however,efferent loop syndrome has been reported in rare cases.Here,we report a case of efferent loop obstruction that occurred after postoperative adhesiolysis of a small-bowel obstruction.The patient had undergone a partial gastrectomy with BillrothⅡanastomosis and gastric ulcer perforation 30 years prior.The efferent loop obstruction was successfully resolved by the insertion of a double pigtail stent.To the best of our knowledge,this is the first case in the literature describing the treatment of efferent loop obstruction.

CMOS analog and mixed-signal phase-locked loops: An overview

CMOS analog and mixed-signal phase-locked loops(PLL)are widely used in varies of the system-on-chips(SoC)as the clock generator or frequency synthesizer.This paper presents an overview of the AMS-PLL,including:1)a brief introduction of the basics of the charge-pump based PLL,which is the most widely used AMS-PLL architecture due to its simplicity and robustness;2)a summary of the design issues of the basic CPPLL architecture;3)a systematic introduction of the techniques for the performance enhancement of the CPPLL;4)a brief overview of ultra-low-jitter AMS-PLL architectures which can achieve lower jitter(<100 fs)with lower power consumption compared with the CPPLL,including the injection-locked PLL(ILPLL),subsampling(SSPLL)and sampling PLL(SPLL);5)a discussion about the consideration of the AMS-PLL architecture selection,which could help designers meet their performance requirements.

An improved arctangent algorithm based on phase-locked loop for heterodyne detection system

We present an ameliorated arctangent algorithm based on phase-locked loop for digital Doppler signal processing,utilized within the heterodyne detection system. We define the error gain factor given by the approximation of Taylor expansion by means of a comparison of the measured values and true values. Exact expressions are derived for the amplitude error of two in-phase & quadrature signals and the frequency error of the acousto-optic modulator. Numerical simulation results and experimental results make it clear that the dynamic instability of the intermediate frequency signals leads to cumulative errors, which will spiral upward. An improved arctangent algorithm for the heterodyne detection is proposed to eliminate the cumulative errors and harmonic components. Depending on the narrow-band filter, our experiments were performed to realize the detectable displacement of 20 nm at a detection distance of 20 m. The aim of this paper is the demonstration of the optimized arctangent algorithm as a powerful approach to the demodulation algorithm, which will advance the signal-to-noise ratio and measurement accuracy of the heterodyne detection system.

Design of radiation hard phase-locked loop at 2.5 GHz using SOS-CMOS

A radiation hard phase-locked loop （PLL） is designed at 2.5 GHz using silicon on sapphire complementary metal-oxide-semiconductor process. Radiation hardness is achieved through improving circuit design without sacrificing real estate. Stability is guaranteed by a fully self-bias architecture. The lock time of PLL is minimized by maximizing the loop bandwidth. Frequency tuning range of voltage controlled oscillator is significantly enhanced by a novel load configuration. In addition, multiple bias stages, asynchronous frequency divider, and silicon on sapphire process jointly make the proposed PLL more radiation hard. Layout of this PLL is simulated by Cadence Spectre RF under both single event effect and total induced dose effect. Simulation results demonstrate excellent stability, lock time 〈 600 ns, frequency tuning range [1.57 GHz, 3.46 GHz], and jitter 〈 12 ps. Through comparison with PLLs in literatures, the PLL is especially superior in terms of lock time and frequency tuning range performances.

A 5.12-GHz LC-based phase-locked loop for silicon pixel readouts of high-energy physics

There is an urgent need for high-quality and high-frequency clock generators for high-energy physics experiments.The transmission data rate exceeds 10 Gbps for a single channel in future readout electronics of silicon pixel detectors.Others,such as time measurement detectors,require a high time resolution based on the time-to-digital readout architecture.A phase-locked loop(PLL)is an essential and broadly used circuit in these applications.This study presents an application-specific integrated circuit of a low-jitter,low-power LC-tank that is PLL fabricated using 55-nm CMOS technology.It includes a 3rd-order frequency synthesis loop with a programmable bandwidth,a divide-by-2 pre-scaler,standard low-voltage differential signaling interfaces,and a current mode logic(CML)driver for clock transmissions.All the d-flip-flop dividers and phase-frequency detectors are protected from single-event upsets using the triple modular redundancy technique.The proposed VCO uses low-pass filters to suppress the noise from bias circuits.The tested LC-PLL covers a frequency locking range between 4.74 GHz and 5.92 GHz with two sub-bands.The jitter measurements of the frequency-halved clock(2.56 GHz)are less than 460 fs and 0.8 ps for the random and deterministic jitters,respectively,and a total of 7.5 ps peak-to-peak with a bit error rate of 10^(-12).The random and total jitter values for frequencies of 426 MHz and 20 MHz are less than 1.8 ps and 65 ps,respectively.The LC-PLL consumed 27 mW for the core and 73.8 mW in total.The measured results nearly coincided with the simulations and validated the analyses and tests.

A LOW POWER TIME-TO-DIGITAL CONVERTER FOR ALL-DIGITAL PHASE-LOCKED LOOP

Time-to-Digital Converter (TDC) is a key block used as the phase/frequency detector in an All-Digital Phase-Locked Loop (ADPLL). Usually, it occupies a large proportion of ADPLL's total power consumption up to about 30% to 40%. In this paper, the detailed power consumption of different components in the TDC is analyzed. A Power Management Block (PMB) is presented for the TDC to reduce its power consumption. A 24-bits TDC core with the proposed PMB is implemented in HJTC 0.18 μm CMOS technology. Simulation results show that up to 84% power reduction is achieved using our proposed technique.

The Singularities of Gravitational Fields of Static Thin Loop and Double Spheres Reveal the Impossibility of Singularity Black Holes

In the classical Newtonian mechanics, the gravity fields of static thin loop and double spheres are two simple but foundational problems. However, in the Einstein’s theory of gravity, they are not simple. In fact, we do not know their solutions up to now. Based on the coordinate transformations of the Kerr and the Kerr-Newman solutions of the Einstein’s equation of gravity field with axial symmetry, the gravity fields of static thin loop and double spheres are obtained. The results indicate that, no matter how much the mass and density are, there are singularities at the central point of thin loop and the contact point of double spheres. What is more, the singularities are completely exposed in vacuum. Space near the surfaces of thin loop and spheres are highly curved, although the gravity fields are very weak. These results are inconsistent with practical experience and completely impossible. By reasonable analogy, black holes with singularity in cosmology and astrophysics are something illusive. Caused by the mathematical description of curved space-time, they do not exist in real world actually. If there are black holes in the universe, they can only be the types of the Newtonian black holes without singularities, rather than the Einstein’s singularity black holes. In order to escape the puzzle of singularity thoroughly, the description of gravity should return to the traditional form of dynamics in flat space. The renormalization of gravity and the unified description of four basic interactions may be possible only based on the frame of flat space-time. Otherwise, theses problems can not be solved forever. Physicists should have a clear understanding about this problem.

Different oxidation routes for lattice oxygen recovery of double-perovskite type oxides LaSrFeCoO6 as oxygen carriers for chemical looping steam methane reforming

Double-perovskite type oxide LaSrFeCoO（LSFCO） was used as oxygen carrier for chemical looping steam methane reforming（CL-SMR） due to its unique structure and reactivity. Two different oxidation routes,steam-oxidation and steam-air-stepwise-oxidation, were applied to investigate the recovery behaviors of the lattice oxygen in the oxygen carrier. The characterizations of the oxide were determined by X-ray diffraction（XRD）, X-ray photoelectron spectroscopy（XPS）, hydrogen temperature-programmed reduction（H-TPR） and scanning electron microscopy（SEM）. The fresh sample LSFCO exhibits a monocrystalline perovskite structure with cubic symmetry and high crystallinity, except for a little impurity phase due to the antisite defect of Fe/Co disorder. The deconvolution distribution of XPS patterns indicated that Co,and Fe are predominantly in an oxidized state(Feand Fe) and(Coand Co), while O 1s exists at three species of lattice oxygen, chemisorbed oxygen and physical adsorbed oxygen. The double perovskite structure and chemical composition recover to the original state after the steam and air oxidation, while the Co ion cannot incorporate into the double perovskite structure and thus form the CoO just via individual steam oxidation. In comparison to the two different oxidation routes, the sample obtained by steam-oxidation exhibits even higher CHconversion, CO and Hselectivity and stronger hydrogen generation capacity.

A new algorithm for diameter of double loop network

Presents a new algorithm for diameter of double loop network(DLN) by which two new classes of infinite families of tight DLN of the known twelve infinie families of tight DLNs, under 3.3 in [1] including eleven are constructed.

A Routing Algorithm for Distributed Optimal Double Loop Computer Networks

A routing algorithm for distributed optimal double loop computer networks is proposed and analyzed. In this paper, the routing algorithm rule is described, and the procedures realizing the algorithm are given. The proposed algorithm is shown to be optimal and robust for optimal double loop. In the absence of failures,the algorithm can send a packet along the shortest path to destination; when there are failures,the packet can bypasss failed nodes and links.

Phase-Locked Loop Based Cancellation of ECG Power Line Interference

Power line(PL)interference is one significant artifact in electrocardiography(ECG)that needs to be reduced to ensure accurate recording of cardiac signals.Because PL interference is non-stationary and has varying frequency,phase,and amplitude in ECG measurement,adaptive techniques are often necessary to track and cancel the interference.In this paper we present a phase-locked loop(PLL)-based adaptive filter to cancel PL interference.The PLL obtains the reference signal that is fed into the adaptive filter to remove the PL interference at the central frequency of 50 Hz.It is found that the technique can effectively cancel PL interference in real ECG signals and,when compared with some existing techniques such as least mean squares(LMS)adaptive filter,the new technique produces better results in terms of signal-to-interference ratio(SIR).

DISTRIBUTED OPTIMAL LOCAL DOUBLE LOOP NETWORK

A distibuted optimal local double loop(DOLDL) network is presented. Emphasis is laid on the topology and distributed routing algorithms for the DOLDL. On the basis of building an abstract model, a set of definitions and theorems are described and proved. An algorithm which can optimize the double loop networks is presented. The optimal values of the topologic parameters for the DOLDL have been obtained by the algorithm, and these numerical results are analyzed. The study shows that the bounds of the optimal diameter (d) and average hop distance (a) for this class of networks are [square-root 3N -2] less-than-or-equal-to d less-than-or-equal-to [square-root 3N+1] and (5N/9(N-1)) (square-root 3N-1.8) < a < (5N/9 (N-1)). (square-root 3N - 0.23), respectively (N is the number of nodes in the network. (3 less-than-or-equal-to N less-than-or-equal-to 10(4)). A class of the distributed routing algorithms for the DOLDL and the implementation procedure of an adaptive fault-tolerant algorithm are proposed. The correctness of the algorithm has been also verified by simulating.

Hybrid phase-locked loop with fast locking time and low spur in a 0.18-μm CMOS process

We propose a novel hybrid phase-locked loop （PLL） architecture for overcoming the trade-off between fast locking time and low spur. To reduce the settling time and meanwhile suppress the reference spurs, we employ a wide-band single-path PLL and a narrow-band dual-path PLL in a transient state and a steady state, respectively, by changing the loop bandwidth according to the gain of voltage controlled oscillator （VCO） and the resister of the loop filter. The hybrid PLL is implemented in a 0.18-μm complementary metal oxide semiconductor （CMOS） process with a total die area of 1.4×0.46 mm2. The measured results exhibit a reference spur level of lower than -73 dB with a reference frequency of 10 MHz and a settling time of 20 μs with 40 MHz frequency jump at 2 GHz. The total power consumption of the hybrid PLL is less than 27 mW with a supply voltage of 1.8 V.

A double closed loop APFC control with feed-forward

In order to improve the steady state performance,dynamic response and power factor of traditional power factor correction(PFC)digital control method and reduce the harmonic distortion of input current,a double closed loop active power factorcorrection(APFC)control method with feed-forward is proposed.Firstly,the small signal model of Boost PFC control systemis built and the system transfer function is deduced,and then the parameters of the main device with Boost topology is estimated.By means of the feed-forward,the system can quickly respond to the change in input voltage.Furthermore,the use ofvoltage loop and current loop can achieve input current and output voltage regulation Simulink modeling shows that this methodcan effectively control the output voltage in case of input voltage largely fluctuating,improve the system dynamic response abilityand input power factor,and reduce the input current harmonic distortion

Modeling and Analysis of Submerged Arc Weld Power Supply Based on Double Closed-Loop Control

According to the soft-switching pulsed SAW (Submerged arc weld) weld power supply based on the double closed-loop constant current control mode, a small signal mathematic model of main circuit of soft-switching SAW inverter was established by applying the method of three-terminal switching device modeling method, and the math-ematic model of double closed-loop phase-shift control system circuit was established by applying the method of state-space averaging method. Dynamic performance of the inverter was analyzed on base of the established math-ematic model, and the tested wave of dynamic performance was shown by experimentation. Research and experimentation show that relation between structure of the power source circuit and dynamic performance of the controlling system can be announced by the established mathematic model, which provides development of power supply and optimized design of controlling parameter with theoretical guidance.

Parameter Design of Current Double Closed Loop for T-Type Three-Level Grid-Connected Inverter

To reduce current harmonics caused by switching frequency,T-type grid-connected inverter topology with LCL filter is adopted.In view of the disadvantages of the slow response speed of the traditional current control and the failure to eliminate the influence of the LCL filter on the grid-connected current by using current PI control alone,a current double closed loop PI current tracking control is proposed.Through the theoretical analysis of the grid-connected inverter control principle,the grid-connected inverter control model is designed,and the transfer functionmodel of each control link is deduced,and the current loop PI regulator is designed at last.The simulation results show that the control strategy is feasible.

Comparative Study of Low-Pass Filter and Phase-Locked Loop Type Speed Filters for Sensorless Control of AC Drives

High quality speed information is one of the key issues in machine sensorless drives,which often requires proper filtering of the estimated speed.This paper comparatively studies typical low-pass filters(LPF)and phase-locked loop(PLL)type filters with respect to ramp speed reference tracking and steady-state performances,as well as the achievement of adaptive cutoff frequency control.An improved LPF-based filter structure with no ramping and steady-state errors caused by filter parameter quantization effects is proposed,which is suitable for applying LPF for sensorless drives of AC machines,especially when fixed-point digital signal processor is selected e.g.in mass production.Furthermore,the potential of adopting PLL for speed filtering is explored.It is demonstrated that PLL type filters can well maintain the advantages offered by the improved LPF.Moreover,it is found that the PLL type filters exhibit almost linear relationship between the cutoff frequency of the PLL filter and its proportional-integral(PI)gains,which can ease the realization of speed filters with adaptive cutoff frequency for improving the speed transient performance.The proposed filters are verified experimentally.The PLL type filter with adaptive cutoff frequency can provide satisfactory performances under various operating conditions and is therefore recommended.