Wide-bandgap devices,such as silicon-carbide metal-oxide-semiconductor field-effect transistors(MOSFETs)and gallium-nitride high electron mobility transistors(HEMTs),exhibit an excellent figure of merits compared to c...Wide-bandgap devices,such as silicon-carbide metal-oxide-semiconductor field-effect transistors(MOSFETs)and gallium-nitride high electron mobility transistors(HEMTs),exhibit an excellent figure of merits compared to conventional silicon devices.Challenges of applying such fast switches include accurate extraction and optimization of parasitics especially when 6high-efficiency operation,all of which require the comprehensive understanding of such switch especially its interaction with peripheral circuits.Particularly for the enhancement-mode GaN HEMTs without the intrinsic body diode,when reverse conducting,its high voltage drop causes a high dead-time loss,which has rarely a concern in silicon devices.This paper focuses on 650V/30~60A enhancement-mode GaN HEMTs provided by GaN Systems,analytically models its switching behaviors,summarizes the impact of parasitics and dead time,and applies it in two DC/DC converters.Systematic design rules are generated not only for soft switching but also for hard switching applications.展开更多
The diode-triggered silicon-controlled rectifier（DTSCR） is widely used for electrostatic discharge（ESD） protection in advanced CMOS process owing to its advantages, such as design simplification, adjustable trigge...The diode-triggered silicon-controlled rectifier（DTSCR） is widely used for electrostatic discharge（ESD） protection in advanced CMOS process owing to its advantages, such as design simplification, adjustable trigger/holding voltage, low parasitic capacitance. However, the multiple-triggering effect in the typical DTSCR device may cause undesirable larger overall trigger voltage, which results in a reduced ESD safe margin. In previous research, the major cause is attributed to the higher current level required in the intrinsic SCR. The related discussions indicate that it seems to result from the current division rule between the intrinsic and parasitic SCR formed in the triggering process. In this letter, inserting a large space into the trigger diodes is proposed to get a deeper insight into this issue. The triggering current is observed to be regularly reduced along with the increased space, which confirms that the current division is determined by the parasitic resistance distributed between the intrinsic and parasitic SCR paths. The theoretical analysis is well confirmed by device simulation and transmission line pulse（TLP） test results. The reduced overall trigger voltage is achieved in the modified DTSCR structures due to the comprehensive result of the parasitic resistance vs triggering current, which indicates a minimized multipletriggering effect.展开更多
文摘Wide-bandgap devices,such as silicon-carbide metal-oxide-semiconductor field-effect transistors(MOSFETs)and gallium-nitride high electron mobility transistors(HEMTs),exhibit an excellent figure of merits compared to conventional silicon devices.Challenges of applying such fast switches include accurate extraction and optimization of parasitics especially when 6high-efficiency operation,all of which require the comprehensive understanding of such switch especially its interaction with peripheral circuits.Particularly for the enhancement-mode GaN HEMTs without the intrinsic body diode,when reverse conducting,its high voltage drop causes a high dead-time loss,which has rarely a concern in silicon devices.This paper focuses on 650V/30~60A enhancement-mode GaN HEMTs provided by GaN Systems,analytically models its switching behaviors,summarizes the impact of parasitics and dead time,and applies it in two DC/DC converters.Systematic design rules are generated not only for soft switching but also for hard switching applications.
基金supported by the Beijing Natural Science Foundation,China(No.4162030)
文摘The diode-triggered silicon-controlled rectifier（DTSCR） is widely used for electrostatic discharge（ESD） protection in advanced CMOS process owing to its advantages, such as design simplification, adjustable trigger/holding voltage, low parasitic capacitance. However, the multiple-triggering effect in the typical DTSCR device may cause undesirable larger overall trigger voltage, which results in a reduced ESD safe margin. In previous research, the major cause is attributed to the higher current level required in the intrinsic SCR. The related discussions indicate that it seems to result from the current division rule between the intrinsic and parasitic SCR formed in the triggering process. In this letter, inserting a large space into the trigger diodes is proposed to get a deeper insight into this issue. The triggering current is observed to be regularly reduced along with the increased space, which confirms that the current division is determined by the parasitic resistance distributed between the intrinsic and parasitic SCR paths. The theoretical analysis is well confirmed by device simulation and transmission line pulse（TLP） test results. The reduced overall trigger voltage is achieved in the modified DTSCR structures due to the comprehensive result of the parasitic resistance vs triggering current, which indicates a minimized multipletriggering effect.
