Effects of source-drain underlaps on the performance of silicon nanowire on insulator transistors

The effects of source-drain underlaps on the performance of a top gate silicon nanowire on insulator transistor are studied using a three dimensional(3D) self-consistent Poisson-Schrodinger quantum simulation. Voltage-controlled tunnel barrier is the device transport physics. The off current, the on/off current ratio, and the inverse subthreshold slope are improved while the on current is degraded with underlap. The physics behind this behavior is the modulation of a tunnel barrier with underlap. The underlap primarily affects the tunneling component of drain current. About 50% contribution to the gate capacitance comes from the fringing electric fields emanating from the gate metal to the source and drain. The gate capacitance reduces with underlap, which should reduce the intrinsic switching delay and increase the intrinsic cut-off frequency. However, both the on current and the transconductance reduce with underlap, and the consequence is the increase of delay and the reduction of cut-off frequency.

Mechanism of floating body effect mitigation via cutting off source injection in a fully-depleted silicon-on-insulator technology

In this paper, the effect of floating body effect （FBE） on a single event transient generation mechanism in fully depleted （FD） silicon-on-insulator （SOI） technology is investigated using three-dimensional technology computer-aided design （3D- TCAD） numerical simulation. The results indicate that the main SET generation mechanism is not carder drift/diffusion but floating body effect （FBE） whether for positive or negative channel metal oxide semiconductor （PMOS or NMOS）. Two stacking layout designs mitigating FBE are investigated as well, and the results indicate that the in-line stacking （IS） layout can mitigate FBE completely and is area penalty saving compared with the conventional stacking layout.

Elevated Source/Drain Engineering by Novel Technology for Fully-Depleted SOI CMOS Devices and Circuits

m thin-film fully-depleted SOI CMOS devices with elevated source/drain structure are fabricated by a novel technology.Key process technologies are demonstrated.The devices have quasi-ideal subthreshold properties;the subthreshold slope of nMOSFETs is 65mV/decade,while that of pMOSFETs is 69mV/decade.The saturation current of 1.2μm nMOSFETs is increased by 32% with elevated source/drain structure,and that of 1.2μm pMOSFETs is increased by 24%.The per-stage propagation delay of 101-stage fully-depleted SOI CMOS ring oscillator is 75ps with 3V supply voltage.

Ge Complementary Tunneling Field-Effect Transistors Featuring Dopant Segregated NiGe Source/Drain

Ge complementary tunneling field-effect transistors（TFETs） are fabricated with the NiGe metal source/drain（S/D） structure. The dopant segregation method is employed to form the NiGe/Ge tunneling junctions of sufficiently high Schottky barrier heights. As a result, the Ge p-and n-TFETs exhibit decent electrical properties of large ON-state current and steep sub-threshold slope（S factor）. Especially, I_d of 0.2 μA/μm is revealed at V_g-V_（th） = V_d = ±0.5 V for Ge pTFETs,with the S factor of 28 mV/dec at 7 K.

FinFET Performance Enhancement by Source/Drain Cavity Structure Optimization

Fin field-effect transistor(FinFET)technology has been introduced to the mainstream complementary metal-oxide semiconductor(CMOS)manufacturing for low-power and highperformance applications.However,advanced FinFET nodes are facing significant challenges to enhance the device performance due to the increasingly prominent parasitic resistance and capacitance.In this study,for the first time,we demonstrate methods of enhancing p-channel FinFET(pFET)performance on a fully integrated advanced FinFET platform via source/drain(S/D)cavity structure optimization.By modulating the cavity depth and proximity around the optimal reference point,we show that the trade-off between the S/D resistance and short channel effect,as well as the impact on the parasitic capacitance must be considered for the S/D cavity structure optimization.An extra process knob of applying cavity implant on the desired cavity structure was also demonstrated to modify the S/D junction profile for device performance enhancement.

Schottky barrier MOSFET structure with silicide source/drain on buried metal

In this paper, we propose a novel Schottky barrier MOSFET structure, in which the silicide source/drain is designed on the buried metal （SSDOM）. The source/drain region consists of two layers of silicide materials. Two Schottky barriers are formed between the silicide layers and the silicon channel. In the device design, the top barrier is lower and the bottom is higher. The lower top contact barrier is to provide higher on-state current, and the higher bottom contact barrier to reduce the off-state current. To achieve this, ErSi is proposed for the top silicide and CoSi2 for the bottom in the n-channel ease. The 50 nm n-channel SSDOM is thus simulated to analyse the performance of the SSDOM device. In the simulations, the top contact barrier is 0.2e V （for ErSi） and the bottom barrier is 0.6 eV （for CoSi2）. Compared with the corresponding conventional Schottky barrier MOSFET structures （CSB）, the high on-state current of the SSDOM is maintained, and the off-state current is efficiently reduced. Thus, the high drive ability （1.2 mA/μm at Vds = 1 V, Vgs = 2 V） and the high Ion/Imin ratio （10^6） are both achieved by applying the SSDOM structure.

Improved power simulation of AlGaN/GaN HEMT at class-AB operation via an RF drain–source current correction method

A new modified Angelov current–voltage characteristic model equation is proposed to improve the drain–source current（Ids） simulation of an Al Ga N/Ga N-based（gallium nitride） high electron mobility transistor（Al Ga N/Ga N-based HEMT） at high power operation. Since an accurate radio frequency（RF） current simulation is critical for a correct power simulation of the device, in this paper we propose a method of Al Ga N/Ga N high electron mobility transistor（HEMT）nonlinear large-signal model extraction with a supplemental modeling of RF drain–source current as a function of RF input power. The improved results of simulated output power, gain, and power added efficiency（PAE） at class-AB quiescent bias of Vgs =-3.5 V, Vds= 30 V with a frequency of 9.6 GHz are presented.

Observation of source/drain bias-controlled quantum transport spectrum in junctionless silicon nanowire transistor

We investigate the influence of source and drain bias voltages(V_(DS))on the quantum sub-band transport spectrum in the 10-nm width N-typed junctionless nanowire transistor at the low temperature of 6 K.We demonstrate that the transverse electric field introduced from V_(DS) has a minor influence on the threshold voltage of the device.The transverse electric field plays the role of amplifying the gate restriction effect of the channel.The one-dimensional(1D)-band dominated transport is demonstrated to be modulated by V_(DS) in the saturation region and the linear region,with the sub-band energy levels in the channel(E_(channel))intersecting with Fermi levels of the source(E_(fS))and the drain(E_(fD))in turn as V_(g) increases.The turning points from the linear region to the saturation region shift to higher gate voltages with V_(DS) increase because the higher Fermi energy levels of the channel required to meet the situation of E_(fD)=E_(channel).We also find that the bias electric field has the effect to accelerate the thermally activated electrons in the channel,equivalent to the effect of thermal temperature on the increase of electron energy.Our work provides a detailed description of the bias-modulated quantum electronic properties,which will give a more comprehensive understanding of transport behavior in nanoscale devices.

A threshold voltage model of short-channel fully-depleted recessed-source/drain(Re-S/D) SOI MOSFETs with high-k dielectric

In this paper, a surface potential based threshold voltage model of fully-depleted（FD） recessed-source/drain（Re-S/D）silicon-on-insulator（SOI） metal-oxide semiconductor field-effect transistor（MOSFET） is presented while considering the effects of high-k gate-dielectric material induced fringing-field. The two-dimensional（2D） Poisson＇s equation is solved in a channel region in order to obtain the surface potential under the assumption of the parabolic potential profile in the transverse direction of the channel with appropriate boundary conditions. The accuracy of the model is verified by comparing the model＇s results with the 2D simulation results from ATLAS over a wide range of channel lengths and other parameters,including the dielectric constant of gate-dielectric material.

Research progresses on Cherenkov and transit-time high-power microwave sources at NUDT

Research progresses on Cherenkov and transit-time high-power microwave(HPM)sources in National University of Defense Technology(NUDT)of China are presented.The research issues are focused on the following aspects.The pulse-shortening phenomenon in O-type Cerenkov HPM devices is suppressed.The compact coaxial relativistic backward-wave oscillators(RBWOs)at low bands are developed.The power efficiency in M-Type HPM tubes without guiding magnetic field increased.The power capacities and power efficiencies in the triaxial klystron amplifier(TKA)and relativistic transit-time oscillator(TTO)at higher frequencies increased.In experiments,some exciting results were obtained.The X-band source generated 2 GW microwave power with a pulse duration of 110 ns in 30 Hz repetition mode.Both L-and P-band compact RBWOs generated over 2 GW microwave power with a power efficiency of over 30%.There is approximately a 75% decline of the volume compared with that of conventional RBWO under the same power capacity conditions.A 1.755 GHz MILO produced 3.1 GW microwave power with power efficiency of 10.4%.A 9.37 GHz TKA produced the 240 MW microwave power with the gain of 34 dB.A 14.3 GHz TTO produced 1 GW microwave power with power efficiency of 20%.

Numerical Analysis of Gate-to-Source Distance Effects in SiC MESFETs

Two-dimensional DC and small-signal analysis of gate-to-source scaling effects in SiC-based high-power field-effect transistors have been performed in this paper. The simulation results show that a downscaling of gate-to-source distance can improve device performance, i.e. enhancing drain current, transconductance, and maximum oscillation frequency. This is associated with the peculiar dynamic of electrons in SiC MESFETs, which lead to a linear velocity regime in the source access region. The variations of gate-to-source capacitance, gate-to-drain capacitance, and cut-off frequency with respect to the change in gate-to-source length have also been studied in detail.

适用于SiC MOSFET的漏源电压积分自适应快速短路保护电路研究

SiC MOSFET因其高击穿电压、高开关速度、低导通损耗等性能优势而被广泛应用于各类电力电子变换器中。然而,由于其短路耐受时间仅为2~7μs,且随母线电压升高而缩短,快速可靠的短路保护电路已成为其推广应用的关键技术之一。为应对不同母线电压下的Si C MOSFET短路故障,文中提出一种基于漏源电压积分的自适应快速短路保护方法(drain-sourcevoltageintegration-basedadaptivefast short-circuit protection method,DSVI-AFSCPM),研究所提出的DSVI-AFSCPM在硬开关短路(hardswitchingfault,HSF)和负载短路(fault under load,FUL)条件下的保护性能,进而研究不同母线电压对DSVI-AFSCPM的作用机理。同时,探究Si CMOSFET工作温度对其响应速度的影响。最后,搭建实验平台,对所提出的DSVI-AFSCPM在发生硬开关短路和负载短路时不同母线电压、不同工作温度下的保护性能进行实验测试。实验结果表明,所提出的DSVI-AFSCPM在不同母线电压下具有良好的保护速度自适应性,即母线电压越高,短路保护速度越快,并且其响应速度受Si CMOSFET工作温度影响较小,两种短路工况下工作温度从25℃变化到125℃,短路保护时间变化不超过90 ns。因此,该文为Si CMOSFET在不同母线电压下的可靠使用提供一定技术支撑。

高压大功率SiC MOSFETs短路保护方法

碳化硅(SiC)MOSFETs短路承受能力弱,研究其短路保护方法成为保障电力电子设备安全运行的重要课题。现有方法大多围绕低压小功率SiC MOSFETs,然而随着电压和功率等级的提升,器件特性有所差异,直接套用以往设计难以实现高压大功率SiC MOSFETs的快速、可靠保护。该文首先详细研究了几种常用短路检测方法;其次基于高压大功率SiC MOSFETs器件特性,深入对比分析了不同短路检测方法的适用性,提出一种阻容式漏源极电压检测和栅极电荷检测相结合的短路保护方法;最后搭建了实验平台验证所提方法的可行性。结果表明,提出的方法在硬开关短路故障(hard switching fault,HSF)下,保护响应时间缩短了1.4μs,短路能量降低了62.5%;且能可靠识别负载短路故障(fault under load,FUL)。

GaN HEMT源漏通道区电阻的自热和准饱和效应模型

GaN HEMT在栅极与源极和漏极之间存在一段通道区域,在等效电路模型中通常等效为一电阻,称为源漏通道区电阻R_(D,S)。准确构建GaN HEMT R_(D,S)模型,对于分析GaN HEMT直流和射频特性,构建GaN HEMT大信号模型具有十分重要的意义。本研究给出考虑自热和准饱和效应的R_(D,S)模型。首先由源漏通道区温度T_(CH)与耗散功率P_(diss)的关系,推导出非线性自热效应模型。进一步基于准饱和效应和Trofimenkoff模型,给出源漏通道区电子漂移速度与电场强度的关系表达式,构建非线性R_(D,S)模型。在环境温度Tamb=300~500 K时,源漏通道区二维电子气2DEG面密度n_(S,acc)(T_(CH))和迁移率μ_(acc)(T_(CH))随T_(CH)的升高而下降,这导致低偏置条件下的源漏通道区电阻R_(D0,S0)随T_(CH)呈非线性增长。将本研究和文献报道的R_(D,S)模型与TCAD(Technology Computer Aided Design)仿真数据进行对比,结果显示:本研究与文献报道的漏通道区电阻RD模型的平均相对误差分别为0.32%和1.78%,均方根误差(RMSE)分别为0.039和0.20Ω;RS模型的平均相对误差分别为0.76%和1.73%,RMSE分别为0.023和0.047Ω。与文献报道的实验数据进行对比,结果显示:本研究与文献RD模型的平均相对误差分别为0.91%和1.59%,RMSE分别为0.012和0.015Ω;RS平均相对误差分别为1.22%和2.77%,RMSE分别为0.0015和0.0034Ω。本研究提出的R_(D,S)模型具有更低的平均相对误差和均方根误差,能够更加准确地表征GaN HEMT线性工作区R_(D,S)随漏源电流I_(DS)的变化。可将本模型用于器件的设计优化,也可作为Spice模型用于电路仿真。

近场声全息重建参数对隔声测量精度的影响

等效源法近场声全息可以开展建筑构件隔声测量的工作。采用近场声全息测量构件隔声量时,重建参数对声场重建结果影响显著。基于对等效源法近场声全息隔声测量理论的分析,利用传声器阵列测得构件表面的复声压信号,通过声场重建得到构件的隔声量和表面法向声强分布。为进一步探究重建参数对等效源法近场声全息隔声测量精度的影响,通过控制变量法在隔声室开展以传统声压法为对比的建筑构件隔声测量实验。结果表明:当等效源面位置从-2 cm变化至-5 cm时,表面法向声强的重建平均误差值由3.9 dB增大至5.6 dB,隔声量的重建平均误差值由5.2 dB增大至6.9 dB,测量误差随等效源面距离而增大,因此等效源面宜靠近声源面;当全息测量面距离为4、8和16 cm时,表面法向声强的重建平均误差值分别为0.6、1.9和5.5 dB,隔声量的重建平均误差值分别为0.9、1.4和4.6 dB,测量误差随全息测量面距离而增大,因此建议全息测量面距离保持在8 cm之内;当等效源点数目与全息面测点数目一致时,与传统声压法差异仅为0.84 dB,当二者数目不一致时,隔声量和表面法向声强平均误差值均增大至4.6~6.8 dB。通过对重建参数进行优选可以有效提高构件隔声测量精度,对实验室测量建筑构件隔声性能与方法有重要借鉴意义,同时在隔声测量技术的实际运用中有较高的参考价值。

油田通井机噪声危害分析与治理

目的针对油田通井机噪声危害的问题,寻求合理的解决方案。方法选择某油田油气井下作业单位的柴油驱动通井机作为研究对象,通过采取振动与噪声测试,分析TJL-12通井机主要噪声源和传播途径,对驾驶舱和发动机舱进行隔声和吸声,对调节阀处进行消声等设计和改造,降低噪声接触水平,使其低于国家职业接触限值要求,改善油气井下作业环境。结果噪声检测结果显示,通井机司钻接触噪声强度由95.2 dB(A)降至84.2 dB(A),低于85 dB(A)的噪声接触限值。结论噪声危害分析和综合治理方案可有效解决油田行业在修井作业时通井机噪声危害控制难题。

二氧化硅气凝胶的研究进展

二氧化硅气凝胶是一种具有高孔隙率、低密度以及低热导率等特性的纳米多孔材料,在保温隔热、环境净化以及生命医学等领域应用广泛。文章对比分析了不同硅源基气凝胶的性能差异,以及改善二氧化硅力学性能的方法,如纤维和聚合物增强二氧化硅气凝胶以及制备柔性二氧化硅气凝胶,介绍了其在不同领域中的应用,并对其未来的发展趋势进行了展望。

珠江源曲靖南盘江污染特征分析及对策措施

南盘江是珠江源头、云南曲靖人民的母亲河,其综合系统治理关系到曲靖的生态环境改善和经济社会的可持续发展。为精准掌握南盘江流域水污染问题,本研究详细分析了水质时空变化,降雨时城区管网溢流情况,沿岸排污口分布及污染物排放、合流制截污管网覆盖及漏损情况,南盘江干流闸坝运行调度情况。结果表明:南盘江流域水质劣Ⅴ类,重度污染,水质旱季劣于雨季,支流劣于干流,下游劣于上游,主要超标因子为NH 3-N和TP;当城区降雨量高于约10 mm时,部分支流白石江等雨水口大量生活污水溢流,雨污合流制难以应对降雨天气;干支流共有排口225个,抽检50个排口水质达标率约24%,超标排放情况普遍;曲靖城区城市建设落后,建成区约30 km 2采用雨污合流制,仍有约40%区域未覆盖截污管网;城区人均水资源量760 m 3,仅为云南人均的15.6%,全国的36%,沿岸闸坝蓄水满足农业灌溉用水需求,闸坝运行调度混乱,河道生态流量无法保障。建议以河长制为抓手,加强工业及城镇生活点源污染治理,优化区域水资源配置,推进河道综合治理、理顺管理机制体制,构建快处高效的治理执行体系,形成全社会参与的南盘江治理局面,方能促进南盘江水生态环境质量持续改善,惠及民生,还河于民。

考虑经济性的北方农村地区低碳清洁取暖策略研究

大力推广清洁取暖是关系国计民生的重要工作,然而清洁取暖不是单纯的能源替代,特别在农村地区,同时需要考虑经济性和可推广性等。为此,提出了加装保温窗帘降低建筑整体热负荷,利用符合生活习惯的电热炕来满足局部热舒适需求,以及引入热泵热风机进行总体环境控制的策略。以山西农村某典型农宅为研究对象,利用TRNSYS对提出的清洁取暖方案进行模拟分析。结果表明,在取暖初期、室外温度最低时、取暖末期3个典型日均能够满足人体舒适性要求;在整个取暖期年运行费用可节约37.9%,费用年值没有显著的差异;同时SO_(2)、NO_(x)、PM_(2.5)和CO_(2)排放量分别降低了99.1%、92.1%、98.9%、89.4%。可为北方农村地区推广清洁取暖提供路线指导。

Al_(2)O_(3)/HfO_(2)双钝化层微波氢终端金刚石MOSFET特性研究

微波氢终端金刚石器件低纵横比会导致较高的关态漏极泄漏电流,从而降低器件可靠性。文章首先提出一种金属-绝缘体-半导体电容模型揭示了漏极泄漏电流的抑制机理,然后利用高介电常数(High-K)顶部钝化层(Upper Passivation Layer,UPL)对漏极泄漏电流进行抑制,最后制备了40/100 nm Al_(2)O_(3)/HfO_(2)双钝化层氢终端金刚石金属-氧化物-半导体场效应晶体管(Metal-Oxide-Semiconductor Field-Effect Transistor,MOSFET)。实验结果表明,顶部钝化100 nm厚HfO_(2)后的氢终端金刚石MOSFET,在纵横比为7.5的情况下实现了约-3×10^(-7)mA/mm的漏极泄漏电流,射频特性测试表明其截止频率和最高振荡频率分别为6.1 GHz和11.1 GHz。以上结果表明,本文提出的Al_(2)O_(3)/HfO_(2)双钝化层氢终端金刚石MOSFET在高可靠和高频应用方面具有重要意义。