A Novel Integrated Circuit Driver for LED Lighting

A novel integrated circuit for driving LED lighting has been proposed, designed and fabricated. Besides the typical parts of LED driver, an integral part was added at the output terminal of error amplifier in the driver. In this way, a novel average current mode can be set up to take the place ordinary peak current control mode. In addition, a BUCK low-level topology was adopted, too. It can be used to drive up to eight 1 W HB LED lights with 350 mA constant current. In this way, the LED driver displays high performance, in which output current with less 1% error and total efficiency as high as 96%. The feasibility of the design has been verified by actual measurement on the fabricated chip.

一种用于光隔离IGBT栅极驱动的智能型LED驱动电路

采用双极型工艺设计了一种智能型高速LED驱动电路,可用于光隔离IGBT栅极驱动芯片的输入驱动。该设计采用一种新型逻辑门结构来实现信号传输、故障反馈以及外部置位等功能,同时达到降低信号传输延迟时间的目的。测试结果表明,在常温条件下,LED驱动电路的输入信号传输延迟时间为70 ns,复位信号有效到故障消除的延迟时间为4.59μs。所设计的驱动电路能够满足光耦隔离IGBT栅极驱动芯片的使用要求。

一种灵活可靠的IGBT驱动电路设计

在当今减碳排放背景下,全控型功率器件IGBT以优异的性能广泛用于各种变流器中,有效可靠的驱动电路对IGBT的安全工作至关重要,特别是大功率应用场合。针对大功率IGBT应用中对驱动电路灵活可靠的要求,设计了一种基于智能集成光耦驱动器ACPL-332J的IGBT驱动保护电路,分析了ACPL-332J的各项参数,并以ACPL-332J为核心设计了驱动电路。以英飞凌FF600R12ME4为应用IGBT,通过双脉冲试验、短路试验验证了设计电路驱动及保护的有效性。

集成结温在线监测功能的IGBT智能驱动器

结温是表征功率器件寿命的重要参数,对功率器件结温进行监测具有重要意义。基于热敏电参数法,选取对温度敏感的电参量饱和导通压降V_(CE(sat))作为研究对象,在IGBT驱动器中集成高精度结温参数测量电路,使系统可在线监测功率器件结温。同时为了得到更加精准的热-电参量对应关系,通过分段拟合的方式对IGBT模块在工作状态下结温与V_(CE(sat))的关系进行数学建模。在此基础上,还设计了相应的退饱和检测电路和分级驱动电路。经过实验验证,最终解决了传统结温测量方式工程应用性差的问题,提高了参数采集精度,将热敏电参数的结温预测误差控制在±5℃以内。

一种40Mbps传输速率的光纤数据接口芯片设计

阐述设计的一种40Mbps光纤数据接口的芯片,传输速率是20Mbps光纤数据接口芯片的1.6倍,传输延时达到20ns,抖动时间稳定在0.04ns,占空比达到44.19%,信号传输能力稳定且输出信号不失真。在此基础上,将芯片和LED封装在一起,该芯片可以为LED稳定提供3.5~4mA的工作电流,降低整体功耗。该芯片适合数字光学数据链接和数字音频接口。

一种BCM Boost PFC电路的VCFF控制策略

临界导通模式Boost功率因素校正(PFC)电路通常采用恒定导通时间(COT)控制策略,导致开关频率的变化与输入电压、输出功率以及电感有关,轻载下过高的开关频率将影响电路的转换效率,故提出一种谷底计数频率反走(VCFF)控制策略。通过检测MOS管两端电压谷底计数,使电路轻载时工作在断续模式,从而降低开关频率以提升轻载效率。实验结果表明,相比于COT控制策略,所提控制策略能够有效提高轻载效率。输入电压为220 Vrms下,10%~50%负载时效率在0.96以上。

一种无桥高增益单级LED驱动电路及其混合控制策略

中小功率的LED驱动电源中,传统两级LED驱动电源存在体积大、成本高以及传统Boost PFC电路在低压输入时导通损耗大等问题。为此提出一种由无桥二次型Boost PFC电路和DC-DC LLC电路集成的无桥高增益单级LED驱动电路,实现了高电压增益、功率开关器件软开关、一套控制电路和高电路转换效率。针对单级电路在电网输入电压变化引起直流母线电压变动范围大等问题,设计一种适用于所提电路的APWM-PFM混合控制策略,并对混合控制原理和控制过程进行详细分析。最后设计一台200 W的实验样机,在输入电压80~120 Vrms范围内,占空比最大为0.5,最大电压增益为6.7,直流母线电压基于网侧特性和LLC电路特性设计在700 V以内,样机的功率因数值均高于0.990,THD均低于15%。在满载条件下,110 Vrms输入时,样机效率为93.20%,相比于传统无桥PFC,电压增益提高了2.21倍,实现了高电压增益和软开关,有效提升了在低压输入条件下的电路转换效率。仿真和实验结果验证了所提出电路和控制方法的有效性。

Influences of Switching Jitter on the Operational Performances of Linear Transformer Drivers-Based Drivers

A whole circuit model of a linear transformer drivers （LTD） module composed of 60 cavities in series was developed in the software PSPICE to study the influence of switching jitter on the operational performances of LTDs. In the model, each brick in each cavity is capable of operating with jitter in its switch. Additionally, the manner of triggering cables entering into cavities was considered. The performances of the LTD module operating with three typical cavity-triggering sequences were simulated and the simulation results indicate that switching jitter affects slightly the peak and starting time of the output current pulse. However, the enhancement in switching jitter would significantly lengthen the rise time of the output current pulse. Without considering other factors, a jitter lower than 10 ns may be necessary for the switches in the LTD module to provide output current parameters with an acceptable deviation.

Numerical Analysis of the Output-Pulse Shaping Capability of Linear Transformer Drivers

Output-pulse shaping capability of a linear transformer driver （LTD） module under different conditions is studied, by conducting the whole circuit model simulation by using the PSPICE code. Results indicate that a higher impedance profile of the internal transmission line would lead to a wider adjustment range for the output current rise time and a narrower adjustment range for the current peak. The number of cavities in series has a positive effect on the output- pulse shaping capability of LTD. Such an improvement in the output-pulse shaping capability can primarily be ascribed to the increment in the axial electric length of LTD. For a triggering time interval longer than the time taken by a pulse to propagate through the length of one cavity, the output parameters of LTD could be improved significantly. The present insulating capability of gas switches and other elements in the LTD cavities may only tolerate a slightly longer deviation in the triggering time interval. It is feasible for the LTD module to reduce the output current rise time, though it is not useful to improve the peak power effectively.

Through-silicon-via crosstalk model and optimization design for three-dimensional integrated circuits

Through-silicon-via （TSV） to TSV crosstalk noise is one of the key factors affecting the signal integrity of three- dimensional integrated circuits （3D ICs）. Based on the frequency dependent equivalent electrical parameters for the TSV channel, an analytical crosstalk noise model is established to capture the TSV induced crosstalk noise. The impact of various design parameters including insulation dielectric, via pitch, via height, silicon conductivity, and terminal impedance on the crosstalk noise is analyzed with the proposed model. Two approaches are proposed to alleviate the TSV noise, namely, driver sizing and via shielding, and the SPICE results show 241 rnV and 379 mV reductions in the peak noise voltage, respectively.

Design and Verification of a High Performance LED Driver with an Efficient Current Sensing Architecture

A high power buck-boost switch-mode LED driver delivering a constant 350 mA with a power efficient current sensing scheme is presented in this paper. The LED current is extracted by differentiating the output capacitor voltage and maintained by a feedback. The circuit has been fabricated in a standard 0.35 μm AMS CMOS process. Measurement results demonstrated a power-conversion efficiency over 90% with a line regulation of 8%/V for input voltage of 3.3 V and current output between 200 mA and 350 mA.

A Review of PVT Compensation Circuits for Advanced CMOS Technologies

The recent high-performance interfaces like DDR2, DDR3, USB and Serial ATA require their output drivers to provide a minimum variation of rise and fall times over Process, Voltage, and Temperature (PVT) and output load variations. As the interface speed grows up, the output drivers have been important component for high quality signal integrity, because the output voltage levels and slew rate are mainly determined by the output drivers. The output driver impedance compliance with the transmission line is a key factor in noise minimization due to the signal reflections. In this paper, the different implementations of PVT compensation circuits are analyzed for cmos45nm and cmos65nm technology processes. One of the considered PVT compensation circuits uses the analog compensation approach. This circuit was designed in cmos45nm technology. Other two PVT compensation circuits use the digital compensation method. These circuits were designed in cmos65nm technology. Their electrical characteristics are matched with the requirements for I/O drivers with respect to DDR2 and DDR3 standards. DDR2 I/O design was done by the Freescale wireless design team for mobile phones and later was re-used for other high speed interface designs. In conclusion, the advantages and disadvantages of considered PVT control circuits are analyzed.

基于磁隔离驱动的双极性Marx脉冲源研制

该文针对脉冲功率技术在食品杀菌处理等领域的双极性高电压应用需求,设计了一种基于磁隔离驱动的全固态双极性Marx脉冲源。该双极性脉冲源主电路采用双Marx型电路拓扑。驱动电路采用磁心传递控制信号,利用磁心堆叠和次级绕组反并联方式,使得系统仅需两路驱动信号即可实现双Marx主电路拓扑中四种开关的控制。驱动电路结构简单可靠,开关同步性高。基于此驱动电路和主电路,筛选了主要器件,开展了相应仿真,最终研制出全固态双极性脉冲源样机,并开展了样机的性能测试。测试结果表明,该脉冲源输出电压为0~±20 kV,脉冲宽度为3~10μs,最大重复频率为200 Hz。脉冲源的输出电压、脉冲宽度、重复频率及正负脉冲间距均灵活可调,并可通过增加Marx模块的数量来实现更高等级的输出电压。

A Hybrid GA-SQP Algorithm for Analog Circuits Sizing

This study presents a hybrid algorithm obtained by combining a genetic algorithm (GA) with successive quadratic sequential programming (SQP), namely GA-SQP. GA is the main optimizer, whereas SQP is used to refine the results of GA, further improving the solution quality. The problem formulation is done in the framework named RUNE (fRamework for aUtomated aNalog dEsign), which targets solving nonlinear mono-objective and multi-objective optimization problems for analog circuits design. Two circuits are presented: a transimpedance amplifier (TIA) and an optical driver (Driver), which are both part of an Optical Network-on-Chip (ONoC). Furthermore, convergence characteristics and robustness of the proposed method have been explored through comparison with results obtained with SQP algorithm. The outcome is very encouraging and suggests that the hybrid proposed method is very efficient in solving analog design problems.

新能源汽车DC/AC变换电路教学模型设计

DC/AC变换电路作为新能源汽车上的核心电路之一,在实车上,由于集成度高、高电压等特性,非常不利于初学者进行学习。本文中设计的DC/AC变换电路教学模型,学生不仅能直观认识其主电路和控制电路的结构,而且还能通过预留的接线端子进行电路再次搭建和测量其关键信号线上的电路参数,进而快速掌握DC/AC变换电路的基本结构和工作原理,为后续实车故障诊断打下较好的基础。

GaN HEMT及GaN栅驱动电路在DToF激光雷达中的应用

DToF(Direct Time-of-Flight)激光雷达通过直接测量激光的飞行时间完成距离测量和地图成像,应用于自动驾驶的DToF激光雷达需要具备更高的分辨率和更宽的检测范围。GaN高电子迁移率晶体管(HEMT)相对于传统Si基功率MOSFET的优异特性使其非常适合应用于自动驾驶中的DToF激光雷达,而GaN HEMT性能的发挥依赖于高速、高驱动能力和高可靠性的GaN栅驱动电路。针对应用于自动驾驶的DToF激光雷达系统,从系统电路到核心元器件,分析了激光二极管驱动电路面临的设计挑战、GaN HEMT的优势以及GaN栅驱动电路面临的设计挑战,并介绍了适合该应用的GaN栅驱动电路。

一种新型SiC MOSFET驱动电路的设计

与传统硅基器件相比,碳化硅(SiC)器件的开关速度得到大幅改善,提高了变换器的功率密度与效率。然而过大的开关频率引起更为严重的栅极串扰问题,造成器件失效。分析了SiC金属-氧化物-半导体场效应晶体管(MOSFET)的开关过程与串扰产生原理,详述其设计过程,分析了外并电容的抑制串扰驱动电路,最后设计出一种带有信号隔离功能的可抑制栅极串扰的负压驱动电路。实验结果表明,所设计的SiC MOSFET驱动电路的驱动波形高低电平分明,而且有效抑制了栅极串扰问题,大幅减小器件的开关延时时间,降低了开关损耗。

基于TMS320F28034两相混合式步进电机驱动电路设计

在设计两相混合式步进电机驱动电路时,为了提高驱动功率、降低驱动电路发热量,提出了一种基于DSP+半桥栅极驱动器的两相混合式步进电机驱动电路的设计方案。选用TMS320F28034作为核心控制器控制PWM信号,4个半桥栅极驱动器组成H桥将PWM信号功率放大,利用H桥下桥臂电阻进行电流采样,实现对两相混合式步进电机的控制。H桥放大电路在提升电路驱动能力的同时,还能降低驱动电路的发热量,该驱动电路可长时间驱动5N.M步进电机运行。

一种高可靠性三相全桥IGBT驱动电路的设计

该文基于X-FAB 1.0μm高压SOI工艺,提出一种适用于600 V高压下的三相全桥IGBT驱动电路,包括输入接口电路、死区时间产生电路、高低压电平位移电路以及其它保护电路。其中针对输入信号可能同时有效的问题,设计了一种可以对输入信号的错误状态进行判断的死区时间产生电路,避免因高、低侧信号同时输入有效电平所造成的错误;高压驱动部分采用一种具有隔离功能的新型电平位移电路,可以减小高低压地电位之间的串扰,有效提高了驱动电路的可靠性。仿真结果表明,高侧浮动电压的范围为0~600 V,能够实现三相高低通路驱动后级的IGBT功率器件,高侧通路电压的输出范围为0~615 V,低侧通路电压的输出范围为0~15 V,驱动电流最大可达0.8 A,高低侧输出信号之间的死区时间为1.2μs,最高工作频率100 kHz。

一种用于GaN HEMT栅驱动片内电源产生电路设计

GaN HEMT功率器件通常用于高频开关频率下(MHZ以上),尤其开关频率达到10 MHZ以上之后,对栅驱动芯片的内部的电源电路设计要求更加苛刻[1]。本文设计了一种带欠压保护功能的LDO电源产生电路,能实时检测电源电压是否处于欠压状态,进而通过关闭电源对芯片进行保护,避免欠压状态对芯片内部电路造成的损害。采用华润微电子0.18 um BCD工艺,完成了电路的仿真设计验证,LDO的输入电压为5 V、输出电压为1.8 V,负载电流在0 mA到20 mA,1 MHz频率跳变时测得下冲电压为500 mV左右,其负载瞬态响应的时间420 ns左右。输入电源电压从欠压到正常跳变,以及正常状态到欠压跳变过程中,欠压保护电路均能很好实现控制信号输出。