This paper presents a novel digital dual-loop control scheme of the PWM(PUlse width modulate)inverter. Deadbeat control technique are employed to enhance the performance. Half switching period delayed sampling and con...This paper presents a novel digital dual-loop control scheme of the PWM(PUlse width modulate)inverter. Deadbeat control technique are employed to enhance the performance. Half switching period delayed sampling and control timing strategy is used to improve the system dynamic response. Simulation and experimental results presented in the paper verified the validity of the proposed control scheme.展开更多
A modified four-dimensional linear active disturbance rejection control(LADRC)strategy is proposed for a dual three-phase permanent magnet synchronous generator(DTP-PMSG)system to reduce cross-coupling between the d a...A modified four-dimensional linear active disturbance rejection control(LADRC)strategy is proposed for a dual three-phase permanent magnet synchronous generator(DTP-PMSG)system to reduce cross-coupling between the d and q axis currents in the d-q subspace and harmonic currents in the x-y subspace.In the d-q subspace,the proposed strategy uses a model-based LADRC to enhance the decoupling effect between the d and q axes and the disturbance rejection ability against parameter variation.In the x-y subspace,the 5th and 7th harmonic current suppression abilities are improved by using quasi-resonant units parallel to the extended state observer of the traditional LADRC.The proposed modified LADRC strategy improved both the steady-state performance and dynamic response of the DTP-PMSG system.The experimental results demonstrate that the proposed strategy is both feasible and effective.展开更多
This work summarizes the structure and operating features of a high-performance 3-stage dual-delay-path (DDP) voltage-controlled ring oscillator (VCRO) with self-biased delay cells for Phase-Locked Loop (PLL) structur...This work summarizes the structure and operating features of a high-performance 3-stage dual-delay-path (DDP) voltage-controlled ring oscillator (VCRO) with self-biased delay cells for Phase-Locked Loop (PLL) structurebased clock generation and digital system driving. For a voltage supply V<sub>DD</sub> = 1.8 V, the resulting set of performance parameters include power consumption P<sub><sub></sub>DC</sub> = 4.68 mW and phase noise PN@1MHz = -107.8 dBc/Hz. From the trade-off involving P<sub>DC</sub> and PN, a system level high performance is obtained considering a reference figure-of-merit ( FoM = -224 dBc/Hz ). Implemented at schematic level by applying CMOS-based technology (UMC L180), the proposed VCRO was designed at Cadence environment and optimized at MunEDA WiCkeD tool.展开更多
文摘This paper presents a novel digital dual-loop control scheme of the PWM(PUlse width modulate)inverter. Deadbeat control technique are employed to enhance the performance. Half switching period delayed sampling and control timing strategy is used to improve the system dynamic response. Simulation and experimental results presented in the paper verified the validity of the proposed control scheme.
基金Supported by the National Science Fund for Distinguished Young Scholars under Grant 52025073 and the Zhenjiang Key Research Program under Grant GY2020011.
文摘A modified four-dimensional linear active disturbance rejection control(LADRC)strategy is proposed for a dual three-phase permanent magnet synchronous generator(DTP-PMSG)system to reduce cross-coupling between the d and q axis currents in the d-q subspace and harmonic currents in the x-y subspace.In the d-q subspace,the proposed strategy uses a model-based LADRC to enhance the decoupling effect between the d and q axes and the disturbance rejection ability against parameter variation.In the x-y subspace,the 5th and 7th harmonic current suppression abilities are improved by using quasi-resonant units parallel to the extended state observer of the traditional LADRC.The proposed modified LADRC strategy improved both the steady-state performance and dynamic response of the DTP-PMSG system.The experimental results demonstrate that the proposed strategy is both feasible and effective.
文摘This work summarizes the structure and operating features of a high-performance 3-stage dual-delay-path (DDP) voltage-controlled ring oscillator (VCRO) with self-biased delay cells for Phase-Locked Loop (PLL) structurebased clock generation and digital system driving. For a voltage supply V<sub>DD</sub> = 1.8 V, the resulting set of performance parameters include power consumption P<sub><sub></sub>DC</sub> = 4.68 mW and phase noise PN@1MHz = -107.8 dBc/Hz. From the trade-off involving P<sub>DC</sub> and PN, a system level high performance is obtained considering a reference figure-of-merit ( FoM = -224 dBc/Hz ). Implemented at schematic level by applying CMOS-based technology (UMC L180), the proposed VCRO was designed at Cadence environment and optimized at MunEDA WiCkeD tool.
