Dual Gate液晶显示屏栅极制程断路缺陷的分析与改善

文章探究了光刻工序的水汽和ITO刻蚀工序的药液结晶对DualGate产品栅极制程的断路影响,通过DOE试验得到影响因子的最佳改善条件,使55寸DualGate产品栅极制程的断路缺陷发生率整体降低36%,为公司带来80.2万元的月度收益,能够对其他高端产品断路缺陷的改善思路、新工艺设备的设计改进,提供参考。

Ambipolar performance improvement of the C-shaped pocket TFET with dual metal gate and gate–drain underlap

Dual-metal gate and gate–drain underlap designs are introduced to reduce the ambipolar current of the device based on the C-shaped pocket TFET(CSP-TFET).The effects of gate work function and gate–drain underlap length on the DC characteristics and analog/RF performance of CSP-TFET devices,such as the on-state current(I_(on)),ambipolar current(I_(amb)),transconductance(g_(m)),cut-off frequency(f_(T))and gain–bandwidth product(GBP),are analyzed and compared in this work.Also,a combination of both the dual-metal gate and gate–drain underlap designs has been proposed for the C-shaped pocket dual metal underlap TFET(CSP-DMUN-TFET),which contains a C-shaped pocket area that significantly increases the on-state current of the device;this combination design substantially reduces the ambipolar current.The results show that the CSP-DMUN-TFET demonstrates an excellent performance,including high I_(on)(9.03×10^(-4)A/μm),high I_(on)/I_(off)(~10^(11)),low SS_(avg)(~13 mV/dec),and low I_(amb)(2.15×10^(-17)A/μm).The CSP-DMUN-TFET has the capability to fully suppress ambipolar currents while maintaining high on-state currents,making it a potential replacement in the next generation of semiconductor devices.

Dual-gate lateral double-diffused metal—oxide semiconductor with ultra-low specific on-resistance

A new high voltage trench lateral double-diffused metal–oxide semiconductor （LDMOS） with ultra-low specific onresistance （R on,sp ） is proposed. The structure features a dual gate （DG LDMOS）： a planar gate and a trench gate inset in the oxide trench. Firstly, the dual gate can provide a dual conduction channel and reduce R on,sp dramatically. Secondly, the oxide trench in the drift region modulates the electric field distribution and reduces the cell pitch but still can maintain comparable breakdown voltage （BV）. Simulation results show that the cell pitch of the DG LDMOS can be reduced by 50% in comparison with that of conventional LDMOS at the equivalent BV; furthermore, R on,sp of the DG LDMOS can be reduced by 67% due to the smaller cell pitch and the dual gate.

Planar split dual gate MOSFET

A new planar split dual gate （PSDG） MOSFET device, its characteristics and experimental results, as well as the three dimensional device simulations, are reported here for the first time. Both theoretical calculation and 3D simulation, as well as the experiment data, show that the two independent split dual gates can provide dynamical control of the device characteristics, such as threshold voltage （Vt） and sub-threshold swing （SS）, as well as the device saturated current. The PSDG MOSFET transistor leakage current （loft） can be reduced as much as 78% of the traditional single gate MOSFET. The PSDG is fabricated and fully compatible with our conventional 0.18 μm logic process flow.

A two-dimensional analytical subthreshold behavior model for junctionless dual-material cylindrical surrounding-gate MOSFETs

A two-dimensional analytical subthreshold behavior model for junctionless dual-material cylindrical surrounding- gate （JLDMCSG） metal-oxide-semiconductor field-effect transistors （MOSFETs） is proposed. It is derived by solving the two-dimensional Poisson＇s equation in two continuous cylindrical regions with any simplifying assumption. Using this analytical model, the subthreshold characteristics of JLDMCSG MOSFETs are investigated in terms of channel electro- static potential, horizontal electric field, and subthreshold current. Compared to junctionless single-material cylindrical surrounding-gate MOSFETs, JLDMCSG MOSFETs can effectively suppress short-channel effects and simultaneously im- prove carrier transport efficiency. It is found that the subthreshold current of JLDMCSG MOSFETs can be significantly reduced by adopting both a thin oxide and thin silicon channel. The accuracy of the analytical model is verified by its good agreement with the three-dimensional numerical simulator ISE TCAD.

A two-dimensional analytical model for channel potential and threshold voltage of short channel dual material gate lightly doped drain MOSFET

An analytical model for the channel potential and the threshold voltage of the short channel dual-material-gate lightly doped drain （DMG-LDD） metal-oxide-semiconductor field-effect transistor （MOSFET） is presented using the parabolic approximation method. The proposed model takes into account the effects of the LDD region length, the LDD region doping, the lengths of the gate materials and their respective work functions, along with all the major geometrical parameters of the MOSFET. The impact of the LDD region length, the LDD region doping, and the channel length on the channel potential is studied in detail. Furthermore, the threshold voltage of the device is calculated using the minimum middle channel potential, and the result obtained is compared with the DMG MOSFET threshold voltage to show the improvement in the threshold voltage roll-off. It is shown that the DMG-LDD MOSFET structure alleviates the problem of short channel effects （SCEs） and the drain induced barrier lowering （DIBL） more efficiently. The proposed model is verified by comparing the theoretical results with the simulated data obtained by using the commercially available ATLASTM 2D device simulator.

Subthreshold current model of fully depleted dual material gate SOI MOSFET

Dual material gate SOI MOSFET with asymmetrical halo can suppress short channel effect and increase carriers transport efficiency. The analytical model of its subthreshold drain current is derived based on the explicit solution of two-dimensional Poisson’s equation in the depletion region. The model takes into consideration the channel length modulation effect and the contribution of the back channel current component. Its validation is verified by comparision with two dimensional device simulator MEDICI.

Drain-induced barrier lowering effect for short channel dual material gate 4H silicon carbide metal-semiconductor field-effect transistor

Sub-threshold characteristics of the dual material gate 4H-SiC MESFET （DMGFET） are investigated and the analytical models to describe the drain-induced barrier lowering （DIBL） effect are derived by solving one- and two- dimensional Poisson＇s equations. Using these models, we calculate the bottom potential of the channel and the threshold voltage shift, which characterize the drain-induced barrier lowering （DIBL） effect. The calculated results reveal that the dual material gate （DMG） structure alleviates the deterioration of the threshold voltage and thus suppresses the DIBL effect due to the introduced step function, which originates from the work function difference of the two gate materials when compared with the conventional single material gate metal-semiconductor field-effect transistor （SMGFET）.

Dual-Gate TFT-LCD抖动算法FRC研究与实现

在TFT-LCD驱动的关键设计技术中,抖动算法FRC(frame rate control)是一种重要的技术。它能够用6 bit source的输出来达到8 bit full color(16.7 M colors)的显示效果,这样可以降低数据传输率以降低功耗,同时可以节省源驱动(Source Driver,SD)芯片的面积。通过分析和实践,提出了针对用于平板电脑的Dual-Gate TFT-LCD屏和翻转方式,需要采用优化的FRC算法提高显示效果。在应用于平板电脑的dual-gate TFT-LCD屏的FRC方案中,分析了传统方案产生周期性竖线的原因,然后提出了改进方案,消除了竖线,提高了显示质量。最后,总结了FRC算法具体需要考虑的因素。

Key technologies for dual high-k and dual metal gate integration

The key technologies for the dual high-k and dual metal gate, such as the electrical optimization of metal insert poly-Si stack structure, the separating of high-k and metal gate of n/pMOS in different regions of the wafer, and the synchronous etching of n/pMOS gate stack, are successfully developed. First, reasonable flat-band voltage and equivalent oxide thickness of pMOS MIPS structure are obtained by further optimizing the HfSiAlON dielectric through incorporating more Al-O dipole at interface between HfSiAlON and bottom SiOx. Then, the separating of high-k and metal gate for n/pMOS is achieved by SC1（NH4OH：H2O2：H2O = 1 ： 1 ： 5） and DHF-based solution for the selective removing of n MOS TaN and Hf Si ON and by BCl3-based plasma and DHF-based solution for the selective removing of pMOS TaN/Mo and HfSiAlON.After that, the synchronous etching of n/pMOS gate stack is developed by utilizing optimized BCl3/SF6/O2/Ar plasma to obtain a vertical profile for TaN and TaN/Mo and by utilizing BCl3/Ar plasma combined with DHF-based solution to achieve high selectivity to Si substrate. Finally, good electrical characteristics of CMOS devices, obtained by utilizing these new developed technologies, further confirm that they are practicable technologies for DHDMG integration.

Analytical Modeling of Dual Material Gate SOI MOSFET with Asymmetric Halo

A dual material gate silicon-on-insulator MOSFET with asymmetrical halo is presented to improve short channel effect and carrier transport efficiency for the first time. The front gate consists of two metal gates with different work functions by making them contacting laterally, and the channel is more heavily doped near the source than in the rest. Using a three-region polynomial potential distribution and a universal boundary condition, a two-dimensional analytical model for the fully depleted silicon-on-insulator MOSFET is developed based on the explicit solution of two-dimensional Poisson’s equation. The model includes the calculation of potential distribution along the channel and subthreshold current. The performance improvement of the novel silicon-on-insulator MOSFET is examined and compared with the traditional silicon-on-insulator MOSFET using the analytical model and two-dimensional device simulator MEDICI. It is found that the novel silicon-on-insulator MOSFET could not only suppress short channel effect, but also increase carrier transport efficiency noticeably. The derived analytical model agrees well with MEDICI.

基于Golden Gate高效构建psiCHECK双荧光素酶报告基因的方法及应用

目的 基于Golden Gate技术构建psiCHECK-CcdB重组双荧光素酶报告载体,并探讨其能否用于RNA干扰(RNA interference, RNAi)药物筛选。方法 通过聚合酶链反应(polymerase chain reaction,PCR)扩增CcdB致死基因、氯霉素基因与Golden Gate组装所需的BsmBI酶切位点,将其克隆至psiCHECK-2载体,构建出重组载体psiCHECK-CcdB。利用2种大肠杆菌DB3.1与DH5α对该载体的致死效率进行检测,选用1 387 bp大小的外源片段克隆至psiCHECK-CcdB载体,检测其连接效率,并验证重组载体能否发挥双荧光素酶报告系统功能,监测目的基因的表达变化。结果 菌落PCR以及测序鉴定psiCHECK-CcdB重组质粒构建成功,该质粒可有效致死无法耐受CcdB毒素的大肠杆菌DH5α菌株,在DB3.1菌株中正常生长。采用Golden Gate的方法可将外源片段简单快速克隆至psiCHECKCcdB载体中,连接效率显著提高且低背景克隆。通过测定双荧光素酶表达强度,证实了小干扰RNA(small interfering RNA,siRNA)靶向性结合目的基因可显著下调荧光素酶的表达,成功发挥双荧光素酶报告基因功能。结论 本研究成功构建了psiCHECK-CcdB重组双荧光素酶报告载体,应用Golden Gate组装技术,简化了实验操作流程,降低了实验成本,具备较高的阳性克隆率与多片段一次性组装的潜力,在RNAi药物筛选领域应用前景广阔。

双栅GaN HEMT生物传感器仿真研究

GaN HEMT因具有优异的高灵敏度、快速响应特性、电学特性和生物相容性,其在生物传感领域具有广泛的应用潜力。为提升GaN HEMT生物传感器直接检测生物分子的灵敏度,提出了一种双栅结构分析模型,并使用Silvaco TCAD工具研究了其电学特性。从漏极电流、阈值电压和电势方面分析了单栅和双栅器件的结构特性,比较了其灵敏度。研究表明,在特定生物分子(尿酸酶、链霉亲和素、蛋白质和胆固醇氧化酶)的检测中,双栅GaN HEMT生物传感器的灵敏度分别比单栅器件高1.55%,2.18%,1.07%和3.3%。其中,增加空腔长度可以为生物分子与生物功能化层(AlGaN)的相互作用提供更多的面积,从而使传感器的灵敏度增加。因此,双栅和较大空腔的GaN HEMT生物传感器器件更适用于高灵敏度的应用。

面向小样本抽取式问答的多标签语义校准方法

小样本抽取式问答任务旨在利用文章给定的上下文片段,抽取出真实的答案片段。其基线模型采用的方法只针对跨度进行学习,缺乏对全局语义信息的利用,在含有多组不同重复跨度的实例中存在着理解偏差等问题。为了解决上述问题,该文利用不同层级的语义提出了一种面向小样本抽取式问答任务的多标签语义校准方法。采用包含全局语义信息的头标签和基线模型中的特殊字符构成多标签进行语义融合,并利用语义融合门来控制全局信息流的引入,将全局语义信息融合到特殊字符的语义信息中。然后,利用语义筛选门对新融入的全局语义信息和该特殊字符的原有语义信息进行保留与更替,实现对标签偏差语义的校准。在8个小样本抽取式问答数据集中的56组实验结果表明:该方法在评价指标F1值上均明显优于基线模型,证明了所提方法的有效性和先进性。

基于双层注意力和深度自编码器的时间序列异常检测模型

目前时间序列通常具有弱周期性以及高度复杂的相关性特征,传统的时间序列异常检测方法难以检测此类异常。针对这一问题,提出了一种新的无监督时间序列异常检测模型(DA-CBG-AE)。首先,使用新型滑动窗口方法,针对时间序列周期性设置滑动窗口大小;其次,采用卷积神经网络提取时间序列高维度空间特征;然后,提出具有堆叠式Dropout双向门循环单元网络作为自编码器的基本结构,从而捕捉时间序列的相关性特征;最后,引入双层注意力机制,进一步提取特征,选择更加关键的时间序列,从而提高异常检测准确率。为了验证该模型的有效性,将DA-CBG-AE与6种基准模型在8个数据集上进行比较。最终的实验结果表明,DA-CBG-AE获得了最优的F1值(0.863),并且其检测性能相比最新的基准模型Tad-GAN高出25.25%。

双芯IGCT浪涌电流鲁棒性研究

作为晶闸管类器件,双芯集成门极换流晶闸管(Dual IGCT)必须具备的抗浪涌电流能力研究鲜见报道。基于多单元集成的器件仿真结构模型,揭示了Dual IGCT在浪涌电流下工作时,总电流在GCT-A部分和GCT-B部分间的分配比例会随晶格温度升高而减小。在此基础上,分析了寿命控制技术对Dual IGCT浪涌鲁棒性的影响。结果表明,增大GCT-B的载流子寿命可以提高器件的浪涌鲁棒性,但同时会增大器件的功耗;而在对GCT-B进行载流子寿命控制时,引入具有较大寿命对温度依赖系数的复合中心,可以有效提高Dual IGCT浪涌电流鲁棒性,同时不影响器件的其他性能。最后,提出了一种工艺成本较低的阳极短路Dual IGCT新结构,其在浪涌电流下的晶格温升与传统的Dual IGCT相比大幅减小(约150 K),呈现出极高的抗浪涌能力。

基于双注意力机制的MSCN-BiGRU的滚动轴承故障诊断方法

针对滚动轴承故障诊断模型在变工况和环境噪声干扰下诊断精度降低的问题,提出一种基于双注意力机制的多尺度卷积网络(dual attention and multi-scale convolutional networks,DAMSCN)与改进的双向门控循环单元(bidirectional gated recurrent unit,BiGRU)组成的故障诊断模型DAMSCN-BiGRU。首先,多尺度特征融合模块使用不同大小的卷积核,获得多种感受野,从而提取到轴承原始振动信号的多尺度特征信息,并根据重要性对其进行自适应融合,然后利用通道注意力和空间注意力组成的双注意力模块(dual attention module,DAM)对多尺度特征进行重新标定,分配注意力权重,削弱融合特征中的冗余特征;然后,增加注意力层和利用分段激活改进BiGRU进而挖掘信号的时域特征,以提高轴承故障诊断的性能;最后,通过Softmax层完成对不同故障的分类。试验结果表明,与其他智能诊断模型相比,DAMSCN-BiGRU在变工况环境下,平均诊断精度达到98.2%,在强噪声背景下仍然有着85.3%的准确率,且在不同程度的噪声强度下效果均优于其他常用模型,有利于促进滚动轴承的智能故障诊断研究和实际应用。

肾积水对轻中度肾损伤者Gates法GFR的影响

目的了解轻中度肾积水对肾动态显像GFR的影响。方法回顾2010年1～12月51例双血浆法GFR(tGFR)在30～90ml/(1.73m2.min)范围内的肾积水患者的肾动态显像,按照tGFR的大小并结合肾脏疾病的分期标准分成正常对照组[90ml(1.73m2.min)≤tGFR<120ml/(1.73m2.min)],轻度[60ml/(1.73m2.min)≤tGFR<90ml/(1.73m2.min)]和中度[30ml/(1.73m2.min)≤tGFR<60ml/(1.73m2.min)]肾损伤3组,并比较体表面积标准化前后Gates法GFR(gGFR)和tGFR间差异和相关性。结果大多数情况下,gGFR均高于tGFR,二者差值范围-35.1～26.1ml/(1.73m2.min);tGFRBSA和gGFRBSA间差值范围-38.3～26.8ml/(1.73m2.min)。无论轻度和中度肾损伤组,还是整体患者中,BSA标准化均可改善tGFR和gGFR间的相关性。BSA标准化后,中度肾损伤组的相关系数可达到0.634(P=0.020),而轻度肾损伤组和整体患者中仅为0.298(P=0.229)和0.543(P=0.002)。结论体表面积标准化Gates法GFR可提高其与双血浆法间的相关性,但评估肾积水伴轻中度肾损伤患者GFR价值有限,应参考双血浆法的定量结果。

CINO双通道结合多头注意力机制藏文情感分类方法

为了解决藏文情感分类任务中现有的模型对文本语义信息理解和深层文本特征提取能力不足的问题,该文使用CINO(Chinese Minority PLM)预训练模型来获取动态词向量,通过TextCNN和BiGRU融合的双通道情感分类模型,分别实现获取文本局部特征和深层全局特征,并引入多头自注意力机制引导模型学习更重要的信息。实验结果表明,该文提出的双通道模型准确率高达92.84%,相较于该文的其他对比模型效果更佳。

基于双编码器表示学习的多模态情感分析

多模态情感分析旨在通过用户上传在社交平台上的视频来判断用户的情感.目前的多模态情感分析研究主要是设计复杂的多模态融合网络来学习模态之间的一致性信息,在一定程度上能够提升模型的性能,但它们大部分都忽略了模态之间的差异性信息所起到的互补作用,从而导致情感分析出现偏差.本文提出了一个基于双编码器表示学习的多模态情感分析模型DERL(dual encoder representation learning),该模型通过双编码器结构学习模态不变表征和模态特定表征.具体来说,我们利用基于层级注意力机制的跨模态交互编码器学习所有模态的模态不变表征,获取一致性信息;利用基于自注意力机制的模态内编码器学习模态私有的模态特定表征,获取差异性信息.此外,我们设计两个门控网络单元对编码后的特征进行增强和过滤,以更好地结合模态不变和模态特定表征,最后在融合时通过缩小不同多模态表示之间的L2距离以捕获它们之间潜在的相似情感用于情感预测.在两个公开的数据集CMU-MOSI和CMU-MOSEI上的实验结果表明该模型优于一系列基线模型.