Drain-induced barrier lowering effect for short channel dual material gate 4H silicon carbide metal-semiconductor field-effect transistor

Sub-threshold characteristics of the dual material gate 4H-SiC MESFET （DMGFET） are investigated and the analytical models to describe the drain-induced barrier lowering （DIBL） effect are derived by solving one- and two- dimensional Poisson＇s equations. Using these models, we calculate the bottom potential of the channel and the threshold voltage shift, which characterize the drain-induced barrier lowering （DIBL） effect. The calculated results reveal that the dual material gate （DMG） structure alleviates the deterioration of the threshold voltage and thus suppresses the DIBL effect due to the introduced step function, which originates from the work function difference of the two gate materials when compared with the conventional single material gate metal-semiconductor field-effect transistor （SMGFET）.

Subthreshold current model of fully depleted dual material gate SOI MOSFET

Dual material gate SOI MOSFET with asymmetrical halo can suppress short channel effect and increase carriers transport efficiency. The analytical model of its subthreshold drain current is derived based on the explicit solution of two-dimensional Poisson’s equation in the depletion region. The model takes into consideration the channel length modulation effect and the contribution of the back channel current component. Its validation is verified by comparision with two dimensional device simulator MEDICI.

A two-dimensional analytical model of fully depleted asymmetrical dual material gate double-gate strained-Si MOSFETs

On the basis of the exact resultant solution of two dimensional Poisson’s equations,a new accurate two-dimensional analytical model comprising surface channel potentials,a surface channel electric field and a threshold voltage for fully depleted asymmetrical dual material gate double-gate strained-Si MOSFETs is successfully developed. The model shows its validity by good agreement with the simulated results from a two-dimensional numerical simulator.Besides offering a physical insight into device physics,the model provides basic design guidance for fully depleted asymmetrical dual material gate double-gate strained-Si MOSFETs.

Design and optimization analysis of dual material gate on DG-IMOS

An impact ionization MOSFET （IMOS） is evolved for overcoming the constraint of less than 60 mV/decade sub-threshold slope （SS） of conventional MOSFET at room temperature. In this work, first, the device performance of the p-type double gate impact ionization MOSFET （DG-IMOS） is optimized by adjusting the device design parameters. The adjusted parameters are ratio of gate and intrinsic length, gate dielectric thickness and gate work function. Secondly, the DMG （dual material gate） DG-IMOS is proposed and investigated. This DMG DG-IMOS is further optimized to obtain the best possible performance parameters. Simulation results reveal that DMG DG-IMOS when compared to DG-IMOS, shows better IoN, ION/IoFF ratio, and RF parameters. Results show that by properly tuning the lengths of two materials at a ratio of 1.5 in DMG DG-IMOS, optimized perform- ance is achieved including ION/IoFF ratio of 2.87 × 10^9 A/μm with/ON as 11.87 × 10^-4 A/μm and transconductance of 1.06× 10^-3 S/μm. It is analyzed that length of drain side material should be greater than the length of source side material to attain the higher transconductance in DMG DG-IMOS.

Dual material gate doping-less tunnel FET with hetero gate dielectric for enhancement of analog/RF performance

In this paper, charge-plasma-based tunnel FET is proposed by employing dual material gate with hetero gate dielectric technique and it is named hetero-dielectric dual material gate doping-less TFET（HD_DMG_DLTFET）. It is compared with conventional doping-less TFET（DLTFET） and dual material gate doping-less TFET（DMG_DLTFET） on the basis of analog and RF performance. The HD_DMG_DLTFET provides better ON state current（I_（ON） =94 μA/ μm）, I_（ON）/I_（OFF）（≈1.36×10^（13））, point（≈3 mV/dec） and average subthreshold slope（AV-SSD40.40 mV/dec）. The proposed device offers low total gate capacitance（C_（gg）/ along with higher drive current. However, with a better transconductance（g_m） and cut-off frequency（f_T）, the HD_DMG_DLTFET can be a good candidate for RF circuitry. The early voltage（V_（EA）/ and output conductance（gd/ are also moderate for the proposed device with comparison to other devices and therefore can be a candidate for analog devices.From all these simulation results and their study, it is observed that HD_DMG_DLTFET has improved analog/RF performance compared to DLTFET and DMG_DLTFET.

3D modelling based comprehensive analysis of high-κ gate stack graded channel dual material trigate MOSFET

The evolution of the traditional metal oxide semiconductor field effect transistor(MOSFET) from planar single gate devices into 3 D multiple gates has led to higher package density and high current drive.However, due to continuous scaling and as a consequent close proximity between source and drain in the nano-regime, these multigate devices have been found to suffer from performance degrading short channel effects(SCEs).In this paper, a three dimensional analytical model of a trigate MOSFET incorporating non-conventional structural techniques like silicon-on-insulator, gate and channel engineering in addition to gate oxide stack is presented.The electrostatic integrity and device capability of suppressing SCEs is investigated by deriving the potential distribution profile using the three dimensional Poisson’s equation along with suitable boundary conditions. The other device parameters like threshold voltage and subthreshold swing are produced from the surface potential model.The validity of the proposed structure is established by the close agreement among the results obtained from the analytical model and simulation results.

The impact of gate misalignment on the analog performance of a dual-material double gate junctionless transistor

The analog performance of gate misaligned dual material double gate junctionless transistor is demonstrated for the first time. The cases considered are where misalignment occurs towards source side and towards drain side. The analog performance parameters analyzed are： transconductance, output conductance, intrinsic gain and cut-off frequency. These figures of merits （FOMs） are compared with a dual material double gate inversion mode transistor under same gate misalignment condition. The impacts of different length of control gate （L 1） for a given gate length （L） are also studied and the optimum lengths La under misalignment condition to have better analog FOMs and high tolerance to misalignment are presented.