Design of dual-edge triggered flip-flops based on quantum-dot cellular automata

Quantum-dot cellular automata (QCA) technology has been widely considered as an alternative to complementary metal-oxide-semiconductor (CMOS) due to QCA's inherent merits.Many interesting QCA-based logic circuits with smaller feature size,higher operating frequency,and lower power consumption than CMOS have been presented.However,QCA is limited in its sequential circuit design with high performance flip-flops.Based on a brief introduction of QCA and dual-edge triggered (DET) flip-flop,we propose two original QCA-based D and JK DET flip-flops,offering the same data throughput of corresponding single-edge triggered (SET) flip-flops at half the clock pulse frequency.The logic functionality of the two proposed flip-flops is verified with the QCADesigner tool.All the proposed QCA-based DET flip-flops show higher performance than their SET counterparts in terms of data throughput.Furthermore,compared with a previous DET D flip-flop,the number of cells,covered area,and time delay of the proposed DET D flip-flop are reduced by 20.5%,23.5%,and 25%,respectively.By using a lower clock pulse frequency,the proposed DET flip-flops are promising for constructing QCA sequential circuits and systems with high performance.

Power-efficient dual-edge implicit pulse-triggered flip-flop with an embedded clock-gating scheme

A novel dual-edge implicit pulse-triggered flip-flop with an embedded clock-gating scheme(DIFF-CGS) is proposed, which employs a transmission-gate-logic(TGL) based clock-gating scheme in the pulse generation stage. This scheme conditionally disables the inverter chain when the input data are kept unchanged, so redundant transitions of delayed clock signals and internal nodes of the latch are all eliminated, leading to low power efficiency. Based on SMIC 65 nm technology, extensive post-layout simulation results show that the proposed DIFF-CGS gains an improvement of 41.39% to 56.21% in terms of power consumption, compared with its counterparts at 10% data-switching activity. Also, full-swing operations in both implicit pulse generation and the static latch improve the robustness of the design. Thus, DIFF-CGS is suitable for low-power applications in very-large-scale integration(VLSI) designs with low data-switching activities.

Anti-Interference Low-Power Double-Edge Triggered Flip-Flop Based on C-Elements

When the input signal has been interfered and glitches occur,the power consumption of Double-Edge Triggered Flip-Flops(DETFFs)will significantly increase.To effectively reduce the power consumption,this paper presents an anti-interference low-power DETFF based on C-elements.The improved C-element is used in this DETFF,which effectively blocks the glitches in the input signal,prevents redundant transitions inside the DETFF,and reduces the charge and discharge frequencies of the transistor.The C-element has also added pull-up and pull-down paths,reducing its latency.Compared with other existing DETFFs,the DETFF proposed in this paper only flips once on the clock edge,which greatly reduces the redundant transitions caused by glitches and effectively reduces power consumption.This paper uses HSPICE to simulate the proposed DETFF and other 10 DETFFs.The findings show that compared with the other 10 types of DETFFs,the proposed DETFF has achieved large performance indexes in the total power consumption,total power consumption with glitches,delays,and power delay product.A detailed analysis of variance indicates that the proposed DETFF features less sensitivity to process,voltage,temperature,and Negative Bias Temperature Instability(NBTI)-induced aging variations.