An improved fully integrated,high-speed,dual-modulus divider

A fully integrated 2n/2n＋1 dual-modulus divider in GHz frequency range is presented. The improved structure can make all separated logic gates embed into correlative D flip-flops completely. In this way, the complex logic functions can be performed with a minimum number of devices and with maximum speed, so that lower power consumption and faster speed are obtained. In addition, the low-voltage bandgap reference needed by the frequency divider is specifically designed to provide a 1.0 V output. According to the design demand, the circuit is fabricated in 0.18 μm standard CMOS process, and the measured results show that its operating frequency range is 1.1- 2.5 GHz. The dual-modulus divider dissipates 1.1 mA from a 1.8 V power supply. The temperature coefficient of the reference voltage circuit is 8.3 ppm/℃ when the temperature varies from -40 to ＋ 125 ℃. By comparison, the dual-modulus divide designed in this paper can possess better performance and flexibility.

基于归一分解的并行多目标Dividing Rectangles算法

多目标优化问题普遍存在且难以解决,目前多采用多目标进化算法进行求解.然而,这些方法通常在种群初始化阶段和进化过程中包含随机操作以保持多样性,导致了其结果不可复现且缺乏全局收敛的理论保证.鉴于此,提出了一种基于归一分解的多目标Dividing Rectangles(DIRECT)算法,首先通过一种可较好捕捉复杂前沿的归一分解方法将原问题分解为一系列子问题,以降低问题计算复杂度;其次,采用Dividing Rectangles算法同时优化分解得到的子问题,并在优化过程中基于全局关联机制将生成的候选解分配给相应的子问题,以更好地保留优秀候选解并提高算法搜索效率;最后,证明了算法的收敛性.此外,为了进一步提高计算效率,提出了一种基于自适应关联迁移策略的多层次多粒度并行方案,并基于该方案对所提出的算法进行了并行化.将所提算法应用于多个基准优化问题,实验结果表明,相比于NSGA-II,所提串行算法能够产生收敛性、多样性更为优越的帕累托最优解集,并行算法可在大规模缩短问题求解时间的同时,进一步提升帕累托前沿近似精度.

Optimization of DC Resistance Divider Up to 1200 kV Using Thermal and Electric Field Analysis

Self-heating and electric field distribution are the primary factors affecting the accuracy of the Ultra High Voltage Direct Current(UHVDC)resistive divider.Reducing the internal temperature rise of the voltage divider caused by self-heating,reducing the maximum electric field strength of the voltage divider,and uniform electric field distribution can effectively improve the UHVDC resistive divider’s accuracy.In this paper,thermal analysis and electric field distribution optimization design of 1200 kV UHVDC resistive divider are carried out:(1)Using the proposed iterative algorithm,the heat dissipation and temperature distribution of the high voltage DC resistive divider are studied,and the influence of the ambient temperature and the power of the divider on the temperature of the insulating medium of the divider is analyzed;(2)Established the finite element models of 1200 kV and 2×600 kV DC resistive dividers,analyzed the influence of the size of the grading ring and the installation position on the maximum electric field strength of the voltage divider,and calculated the impact of the shielding resistor layer on the vicinity of the measuring resistor layer.The research indicates that:(1)The temperature of the insulating medium is linearly related to the horsepower of the voltage divider and the ambient temperature;(2)After the optimized design of the electric field,the maximum electric field strength of the 1200 kV DC resistive divider is reduced to 1471 V/mm,which is about 24% lower than that of the unoptimized design;(3)Installing the shielding resistor layer can significantly improve the electric field near the measuring resistor layer.This paper has an important reference function for improving the accuracy of the UHVDC resistive divider.

A Miniaturized Broadband Wilkinson Power Divider Using Micro-Strip Branch Lines

A miniaturized broadband Wilkinson power divider is proposed. Micro-strip branch lines are introduced to replace multiple resistors used in multi-stage Wilkinson power dividers to increase the bandwidth of single-stage Wilkinson power dividers. To demonstrate its performance, an improved single-stage Wilkinson power divider with four micro-strip branch lines was designed. Simulated results show that the insert loss is better than 3.2 dB, the input return loss, output return loss, and isolation are better than 15 dB respectively, across a 76% bandwidth from 18 to 40 GHz. .

Analysis of Mobile and Internet Network Coverage: Propagation of Electromagnetic Waves and Concept of Digital Divide in Burundi

Mobile and Internet network coverage plays an important role in digital transformation and the exploitation of new services. The evolution of mobile networks from the first generation (1G) to the 5th generation is still a long process. 2G networks have developed the messaging service, which complements the already operational voice service. 2G technology has rapidly progressed to the third generation (3G), incorporating multimedia data transmission techniques. It then progressed to fourth generation (4G) and LTE (Long Term Evolution), increasing the transmission speed to improve 3G. Currently, developed countries have already moved to 5G. In developing countries, including Burundi, a member of the East African Community (ECA) where more than 80% are connected to 2G technologies, 40% are connected to the 3G network and 25% to the 4G network and are not yet connected to the 5G network and then still a process. The objective of this article is to analyze the coverage of 2G, 3G and 4G networks in Burundi. This analysis will make it possible to identify possible deficits in order to reduce the digital divide between connected urban areas and remote rural areas. Furthermore, this analysis will draw the attention of decision-makers to the need to deploy networks and coverage to allow the population to access mobile and Internet services and thus enable the digitalization of the population. Finally, this article shows the level of coverage, the digital divide and an overview of the deployment of base stations (BTS) throughout the country to promote the transformation and digital inclusion of services.

A Programmable 2.4GHz CMOS Multi-Modulus Frequency Divider

A programmable multi-modulus frequency divider is designed and implemented in a 0. 35μm CMOS process. The multi-modulus frequency divider is a single chip with two dividers in series,which are divided by 4 or 5 prescaler and by 128-255 multi-modulus frequency divider. In the circuit design, power and speed trade-offs are analyzed for the prescaler, and power optimization techniques are used according to the input frequency of each divider cell for the 128-255 multimodulus frequency divider. The chip is designed with ESD protected I/O PAD. The dividers chain can work as high as 2.4GHz with a single ended input signal and beyond 2.6GHz with differential input signals. The dual-modulus prescaler consumes 11mA of current while the 128-255 multi-modulus frequency divider consumes 17mA of current with a 3.3V power supply. The core area of the die without PAD is 0.65mm × 0.3mm. This programmable multi-modulus frequency divider can be used for 2.4GHz ISM band PLL-based frequency synthesizers. To our knowledge, this is the first reported multi-modulus frequency divider with this structure in China.

Integrated Low-Power CMOS VCO and Its Divide-by-2 Dividers

An integrated low power CMOS VCO and its divide by 2 dividers for WLAN transceivers are presented.The VCO is based on on chip symmetrical spiral inductor and differential diode and the divide by 2 dividers are based on the ILFD technique.Due to differential LC tanks and ILFD techniques,power consumption is low.The circuit is implemented in a 0 18μm CMOS process.Measurements show the proposed circuit could produce 3 6/1 8GHz dual band LO signals with a wide tuning range and low phase noise.1 8GHz LO signals are quadrature.It consumes 5mA at V DD =1 5V.The size of die area is only 1 0mm×1 0mm.

Low Jitter,Dual-Modulus Prescalers for RF Receivers

Dual-modulus prescalers （DMP） for RF receivers are studied. An improved D-latch is proposed to increase the speed and the driving capability of the DMP. A novel D-latch architecture integrated with ‘OR＇ logic is proposed to decrease the complexity of the circuit. A divided-by-16/17 DMP for application in a digital video broadcasting-terrestrial receiver is realized with a TSMC 0.18μm mixed-signal CMOS process. The programmable ＆ pulse swallow divider in this receiver is designed with a 0.18μm CMOS standard cell library and realized in the same process. The measured results show that the DMP has an output jitter of less than 0.03% and works well with the programmable ＆ pulse swallow divider.

0.18μm CMOS programmable frequency divider design for DVB-T

The implementation of a programmable frequency divider, which is one of the components of the phase-locked loop （PLL） frequency synthesizer for digital video broadcastingterrestrial （DVB-T） and other modem communication systems, is presented. By cooperating with a dual-modulus prescaler, this divider can realize an integer frequency division from 926 to 1 387. Besides the traditional standard cell design flow, such as logic synthesis, placement and routing, the interactions between front-end and back-end are also considered to optimize the design flow under deep submicron technology. By back-annotating the back-end information to front-end design, a custom wire-load model is created which is more practical compared with the default model. This divider has been fabricated in TSMC 0. 18μm CMOS technology using Artisan standard cell library. The chip area is 675 μm × 475 μm and the power consumption is about 2 mW under a 1.8 V power supply. Measurement results show that it works correctly and can realize a frequency division with high precision.

An 8.5GHz 1∶8 Frequency Divider in 0.35μm CMOS Technology

An 1∶8 frequency divider is designed and realized in a 0 35μm standard CMOS technology.The chip consists of three stages of 1∶2 divider cells,which are constructed with source couple logic (SCL) flip flops.By revising the traditional topology of SCL flip flop,a divider with better performances is got.The results of measurement show that the whole chip achieves the frequency division at more than 8 5GHz.Each 1∶2 divider consumes about 11mW from a 3 3V supply.The divider can be used in RF and optic fiber transceivers and other high speed systems.

The Art of Power Dividing:A Review for State-of-the-Art Planar Power Dividers

In this paper,massive state-of-theart planar power dividers are presented and discussed. The innovations of these superiorly-performanced power dividers lie in the performance breakthrough,physical configurations and function integrations. Eventually,based on the trend presented,the future of the power dividers is predicted. This paper might have inspiration significance to illuminate the way for the development of power dividers.

Design of a Frequency Divider with Reduced Complexity Based on a Resonant Tunneling Diode

A novel edge-triggered D-flip-flop based on a resonant tunneling diode （RTD） is proposed and used to construct a binary frequency divider. The design is discussed in detail and the performance of the circuit is verified using SPICE. Relying on the nonlinear characteristics of RTD,we reduced the number of components used in our DFF circuit to only half of that required using conventional CMOS SCFL technology.

A Low Power,High Sensitivity SiGe HBT Static Frequency Divider up to 90 GHz for Millimeter-Wave Application

A layout and connection optimization for static frequency divider is presented. The layout optimization provides a new circle topology transistors placement and reasonable connection structure, which reduces the parasitic effectively and enables self-oscillation frequency enhancement. Besides, bandwidth enhancement techniques based on a center-tap capacitor in input balun design and inductive peaking in latch design are adopted to improve further high frequency performance with low power consumption. As a proof of concept, design of a divide-by-2 static frequency divider in 0.13 μm SiGe BiCMOS technology is reported. With single-ended input clock signal, the divider is measured to be operated from 40 to 90 GHz. Phase noise measurements of a 90 GHz input clock signal indicate ideal behavior with no measurable noise contribution from the divider. The divider followed by a buffer that can deliver more than-10 dBm output power, which is sufficient to drive succeeding stage. To the author's knowledge, the divider exhibits a competitive power dissipation and the highest FOM among silicon based frequency dividers that operating higher than 70 GHz.

Design of 0.18 μm CMOS programmable frequency divider based on standard cells

The design of a programmable frequency divider, which is one of the components of the phase-locked loop （PLL） frequency synthesizer for transmitter and receiver in IEEE 802. 11 a standard, is investigated. The main steps in very large-scale integration （VLSI） design flow such as logic synthesis, floorplan and placement ＆ routing （P ＆ R） are introduced. By back-annotating the back-end information to the front-end design, the custom wire-load model is created and used for optimizing the design flow under deep submicron technology. The programmable frequency divider is implemented based on Artisan TSMC （Taiwan Semicoductor Manufacturing Co. Ltd. ）0. 18μm CMOS （complementary metal-oxide-semiconductor） standard cells and fabricated. The Chip area is 1 360. 5μm^2 and can work in the range of 100 to 200 MHz. The measurement results indicate that the design conforms to the frequency division precision.

Compact UWB Power Divider, Analysis and Design

In this paper, two ultra-wide band power dividers are introduced. Compact equal power divider is considered firstly where an extended transmission lines and double open stubs are used in order to increase the bandwidth. Secondly, an unequal UWB power divider is introduced where multi-stage impedance is used. The proposed power dividers are fabricated and measured. The overall sizes of the proposed power dividers are 11.37 × 17.87 mm2 for the equal one and 12.13 × 29.03 mm2 for the unequal power divider. The simulated results are compared with the measured results and good agreement is obtained.

A power divider based on a new kind of composite right/left-handed transmission line (CRLH TL) unit

A new power divider, composed of a novel composite right/left-handed (CRLH) transmission line (TL) unit, is proposed. The properties of the power divider based on four CRLH TL unit cells are investigated theoretically. By adjusting the parameters of the capacitors and the inductors, the power divider shows perfectly symmetric power division at 5.13 GHz, return loss up to ?24 dB, with the transmitted power being close to ?3.1 dB. The phenomena are demonstrated by simulation results. Being compact in size and low-cost, the proposed power divider is very suitable for microwave and millimeter wave integrated circuits.

A fractional frequency divider based on phase switching and negative feedback delta-sigma modulator for MMMS applications

A fractional frequency divider based on phase switching and negative feedback delta-sigma modulator(NF-DSM) is presented. The phase switching circuit, realized by switching 8 signals generated by a divider-by-4 circuit, is adopted to reduce the frequency division step. The NF-DSM, which can obtain smooth output spectra, is proposed to generate the fractional part of the division ratio, moreover, the integer part of the division ratio is realized by a divider-by-2/3 circuit chain. Fabricated in TSMC 0.18 μm RF CMOS technology, the fractional frequency divider achieves a measured operation frequency from 0.5 GHz to 8 GHz. With a 1.8 V supply voltage, the maximum current consumption of the whole divider is 17.5 mA, and the chip area is 0.58 mm^2, including the pads.

INJECTION-LOCKED DIVIDER

An injection-Locked divider(ILD)can provide good synchronization at lower inputsignal to noise ratio,which is its advantage over other types of divider.The general expressionof phase equation and equivalent model are presented for the ILD with an input additive noise.In the absence of noise the performance of the phase-modulated signal through the ILD andsynchronous ranges of the ILD are given.The effects of the additive noise on the ILD arediscuued.The injection-locked amplifier(ILA)is only a particular case in which n=1,thereforethe given results arc applicable to the ILA.

Residual Phase Noise and Time Jitters of Single-Chip Digital Frequency Dividers

In this paper, we demonstrate the residual phase noise of a few microwave frequency dividers which usually limit the performance of frequency synthesizers. In order to compare these dividers under different operation frequencies, we calculate additional time jitters of these dividers by using the measured phase noise. The time jitters are various from -0.1 fs to 43 fs in a bandwidth from 1 Hz to 100 Hz in dependent of models and operation frequencies. The HMC series frequency dividers exhibit outstanding performance for high operation frequencies, and the time jitters can be sub-fs. The time jitters of SP8401, MC10EP139, and MC100LVEL34 are comparable or even below that of HMC series for low operation frequencies.

A new type of Wilkinson dual-frequency power divider with symmetrical transmission line stubs

To realize equal power splitting at two arbitrary gigahertz-frequencies, this paper presents a new type of Wilkinson dual frequency power divider, consisting of three-section transmission lines and a series RLC(resistor, inductor and capacitor)circuit. By equating the [ABCD] matrix of the proposed circuit to that of the quarter-wave impedance transformer, coupled with even/odd mode analyses, the design equations of the proposed network are derived. For verification, two dual-frequency power dividers with dual-band operating frequencies at 0.6 GHz and 3.0 GHz, and 3.8 GHz and 10 GHz respectively are designed and simulated. Simulation results show that the dual-band ratio of the proposed power divider can be as large as 5. Comparisons of the simulation results at X-band and S-band with different power dividers indicate that the proposed dual-band power divider performs better under the scenario of the upper operating frequency extending to X-band.