期刊文献+
共找到1篇文章
< 1 >
每页显示 20 50 100
A fast-locking all-digital delay-locked loop for phase/delay generation in an FPGA
1
作者 陈柱佳 杨海钢 +1 位作者 刘飞 王瑜 《Journal of Semiconductors》 EI CAS CSCD 北大核心 2011年第10期139-146,共8页
A fast-locking all-digital delay-locked loop(ADDLL) is proposed for the DDR SDRAM controller interface in a field programmable gate array(FPGA).The ADDLL performs a 90°phase-shift so that the data strobe(DQS... A fast-locking all-digital delay-locked loop(ADDLL) is proposed for the DDR SDRAM controller interface in a field programmable gate array(FPGA).The ADDLL performs a 90°phase-shift so that the data strobe(DQS) can enlarge the data valid window in order to minimize skew.In order to further reduce the locking time and to prevent the harmonic locking problem,a time-to-digital converter(TDC) is proposed.A duty cycle corrector(DCC) is also designed in the ADDLL to adjust the output duty cycle to 50%.The ADDLL,implemented in a commercial 0.13μm CMOS process,occupies a total of 0.017 mm^2 of active area.Measurement results show that the ADDLL has an operating frequency range of 75 to 350 MHz and a total delay resolution of 15 ps.The time interval error(TIE) of the proposed circuit is 60.7 ps. 展开更多
关键词 all digital DLL DDR SDRAM controller time-to-digital converter duty cycle corrector DCDL FPGA
原文传递
上一页 1 下一页 到第
使用帮助 返回顶部