Hardware/software partitioning based on dynamic combination of maximum entropy and chaos optimization algorithm

This paper presents an algorithm that combines the chaos optimization algorithm with the maximum entropy ( COA-ME) by using entropy model based on chaos algorithm,in which the maximum entropy is used as the second method of searching the excellent solution. The search direction is improved by chaos optimization algorithm and realizes the selective acceptance of wrong solution. The experimental result shows that the presented algorithm can be used in the partitioning of hardware/software of reconfigurable system. It effectively reduces the local extremum problem,and search speed as well as performance of partitioning is improved.

Scheduling Algorithm Based on Storage Capacity of Communication in Hardware/Software Integrated System

In this paper, the storage capacity of communication among cores and processors is taken into account and a maximum D-value-first algorithm is proposed. By improving the hardware parallelism in the task execution process, the maximum storage requirements for communication are minimized. Experimental results with various directed acyclic graph models showed that compared with the earliest-task-first algorithm, the storage requirements for communication were reduced by 22.46%, on average, while the average of makespan only increased by 0.82%,.

New Approach for Hardware/Software Embedded System Conception Based on the Use of Design Patterns

This paper deals with a new hardware/software embedded system design methodology based on design pattern approach by development of a new design tool called smartcell. Three main constraints of embedded systems design process are investigated: the complexity, the partitioning between hardware and software aspects and the reusability. Two intermediate models are carried out in order to solve the complexity problem. The partitioning problem deals with the proposed hardware/software partitioning algorithm based on Ant Colony Optimisation. The reusability problem is resolved by synthesis of intellectual property blocks. Specification and integration of an intelligent controller on heterogeneous platform are considered to illustrate the proposed approach.

Solving Hardware/Software Partitioning via a Discrete Dynamic Convexized Method

Hardware/software partitioning is an important step in the design of embedded systems. In this paper, the hardware/software partitioning problem is modeled as a constrained binary integer programming problem, which is further converted equivalently to an unconstrained binary integer programming problem by a penalty method. A local search method, HSFM, is developed to obtain a discrete local minimizer of the unconstrained binary integer programming problem. Next, an auxiliary function, which has the same global optimal solutions as the unconstrained binary integer programming problem, is constructed, and its properties are studied. We show that applying HSFM to minimize the auxiliary function can escape from previous local optima by the increase of the parameter value successfully. Finally, a discrete dynamic convexized method is developed to solve the hardware/software partitioning problem. Computational results and comparisons indicate that the proposed algorithm can get high-quality solutions.

A Novel Hardware/Software Partitioning Method Based on Position Disturbed Particle Swarm Optimization with Invasive Weed Optimization

With the development of the design complexity in embedded systems, hardware/software （HW/SW） partitioning becomes a challenging optimization problem in HW/SW co-design. A novel HW/SW partitioning method based on position disturbed particle swarm optimization with invasive weed optimization （PDPSO-IWO） is presented in this paper. It is found by biologists that the ground squirrels produce alarm calls which warn their peers to move away when there is potential predatory threat. Here, we present PDPSO algorithm, in each iteration of which the squirrel behavior of escaping from the global worst particle can be simulated to increase population diversity and avoid local optimum. We also present new initialization and reproduction strategies to improve IWO algorithm for searching a better position, with which the global best position can be updated. Then the search accuracy and the solution quality can be enhanced. PDPSO and improved IWO are synthesized into one single PDPSO-IWO algorithm, which can keep both searching diversification and searching intensification. Furthermore, a hybrid NodeRank （HNodeRank） algorithm is proposed to initialize the population of PDPSO-IWO, and the solution quality can be enhanced further. Since the HW/SW communication cost computing is the most time-consuming process for HW/SW partitioning algorithm, we adopt the GPU parallel technique to accelerate the computing. In this way, the runtime of PDPSO-IWO for large-scale HW/SW partitioning problem can be reduced efficiently. Finally, multiple experiments on benchmarks from state-of-the-art publications and large-scale HW/SW partitioning demonstrate that the proposed algorithm can achieve higher performance than other algorithms.

New Model and Algorithm for Hardware/Software Partitioning

This paper focuses on the algorithmic aspects for the hardware/software （HW/SW） partitioning which searches a reasonable composition of hardware and software components which not only satisfies the constraint of hardware area but also optimizes the execution time. The computational model is extended so that all possible types of communications can be taken into account for the HW/SW partitioning. Also, a new dynamic programming algorithm is proposed on the basis of the computational model, in which source data, rather than speedup in previous work, of basic scheduling blocks are directly utilized to calculate the optimal solution. The proposed algorithm runs in O（n·A） for n code fragments and the available hardware area A. Simulation results show that the proposed algorithm solves the HW/SW partitioning without increase in running time, compared with the algorithm cited in the literature.

RR-SC:边缘设备中基于随机计算神经网络的运行时可重配置框架

随着人工智能民主化的发展,深度神经网络已经被广泛地应用于移动嵌入式设备上,例如智能手机和自动驾驶领域等.随机计算作为一种新兴的、有前途的技术在执行机器学习任务时使用简单的逻辑门而不是复杂的二进制算术电路.它具有在资源(如能源、计算单元和存储单元等)受限的边缘设备上执行深度神经网络低能耗、低开销的优势.然而,之前的关于随机计算的工作都仅仅设计一组模型配置并在固定的硬件配置上实现,忽略了实际应用场景中硬件资源(如电池电量)的动态改变,这导致了低硬件效率和短电池使用时间.为了节省电池供电的边缘设备的能源,动态电压和频率调节技术被广泛用于硬件重配置以延长电池的使用时间.针对基于随机计算的深度神经网络,创新性地提出了一个运行时可重配置框架,即RR-SC,这个框架首次尝试将硬件和软件的重配置相结合以满足任务的时间约束并最大限度节省能源.RR-SC利用强化学习技术可以一次性生成多组模型配置,同时满足不同硬件配置(即不同的电压/频率等级)下的准确率要求.RR-SC得到的解具有最好的准确率和硬件效率权衡.同时,多个模型配置运行时在同一个主干网络上进行切换,从而实现轻量级的软件重配置.实验结果表明,RRSC可以在110 ms内进行模型配置的轻量级切换,以保证在不同硬件级别上所需的实时约束.同时,它最高可以实现7.6倍的模型推理次数提升,仅造成1%的准确率损失.

An efficient GPU-based parallel tabu search algorithm for hardware/software co-design

Hardware/software partitioning is an essential step in hardware/software co-design.For large size problems,it is difficult to consider both solution quality and time.This paper presents an efficient GPU-based parallel tabu search algorithm(GPTS)for HW/SW partitioning.A single GPU kernel of compacting neighborhood is proposed to reduce the amount of GPU global memory accesses theoretically.A kernel fusion strategy is further proposed to reduce the amount of GPU global memory accesses of GPTS.To further minimize the transfer overhead of GPTS between CPU and GPU,an optimized transfer strategy for GPU-based tabu evaluation is proposed,which considers that all the candidates do not satisfy the given constraint.Experiments show that GPTS outperforms state-of-the-art work of tabu search and is competitive with other methods for HW/SW partitioning.The proposed parallelization is significant when considering the ordinary GPU platform.

Hardware-Software Collaborative Techniques for Runtime Profiling and Phase Transition Detection

Dynamic optimization relies on runtime profile information to improve the performance of program execution. Traditional profiling techniques incur significant overhead and are not suitable for dynamic optimization. In this paper, a new profiling technique is proposed, that incorporates the strength of both software and hardware to achieve near-zero overhead profiling. The compiler passes profiling requests as a few bits of information in branch instructions to the hardware, and the processor executes profiling operations asynchronously in available free slots or on dedicated hardware. The compiler instrumentation of this technique is implemented using an Itanium research compiler. The result shows that the accurate block profiling incurs very little overhead to the user program in terms of the program scheduling cycles. For example, the average overhead is 0.6% for the SPECint95 benchmarks. The hardware support required for the new profiling is practical. The technique is extended to collect edge profiles for continuous phase transition detection. It is believed that the hardware-software collaborative scheme will enable many profile-driven dynamic optimizations for EPIC processors such as the Itanium processors.

软件定义测控系统体系架构与关键技术

为了满足快速变化的民商航天测控需求和小卫星及大型星座的快速发展导致的测控任务爆炸式增长需求,将软件定义技术这一被认为改变游戏规则的革命性技术,从互联网行业引入航天测控系统,提出了软件定义航天测控系统体系架构,实现测控系统新一轮技术革新。文章首先分析了传统航天测控系统体系架构及存在问题,其次讨论了软件定义航天测控系统具有层次化设计标准,应用接口开放,系统集中控制,基础资源可灵活重组等技术特征。随后分析了该体系架构的优势及标准接口与规范、软件定义射频前端、软件定义信道和软件定义基带4项关键技术,并对软件定义测控系统发展作出了展望。研究结果表明相比传统测控系统软件定义航天测控系统架构更能满足日益发展的航天事业对测控资源的需求。

地下位移三维测量系统低功耗设计

为了解决地下位移三维监测系统供电成本高的问题,文中从系统级和体系结构级等角度对地下位移三维测量系统进行低功耗设计,延长该系统的工作时间。为最大程度地降低该系统的功耗,分别从器件的选择、电路的硬件改进和多电源域等方面采取硬件低功耗措施。通过动态电源管理的方式对各模块进行分时分区供电的软件低功耗优化设计,实现该检测系统的低功耗设计,减少电池电量的消耗。实验结果表明,所设计系统的每个传感单元休眠时电流均降低至80μA,工作一个周期消耗的电量仅为0.00512 mA·h,相对于原系统减少20.95%,在无外部充电的情况下可连续工作约113天,满足在极端条件下长时间工作的需求。

基于SOA的车身控制器设计

随着车辆功能逐渐增多,用户需求不停更新,车辆软件需要快速迭代才能给用户更好的服务体验,更快的功能体验,真正满足千人千面的需求,从分布式EE架构转变为现在的中央计算加区域控制的架构,以SOA的形式实现软硬解耦,将更多的功能以原子服务的封装集中到车身控制器(BCM),根据动态配置进行不同服务的调用。本文从整车架构、BCM的功能定义、原子服务划分讲述BCM的原子服务设计。

一种基于遗传算法的硬件/软件划分方法

文中采用相邻块通信划分模型及由单处理器和专用硬件构件组成的目标结构 ,解决了硬件约束条件下系统执行速度的优化问题 .与贪心算法相比 ,该方法可在合理的时间内为嵌入式系统寻找到满意的解决方案 .

嵌入式粗颗粒度可重构处理器的软硬件协同设计流程

面向多媒体应用的可重构处理器架构由主处理器和动态配置的可重构阵列(Reconfigurable Cell Array,RCA)组成.协同设计流程以循环流水线和流水线配置技术为基础,采用启发式算法对应用中较大的关键循环进行了软硬件划分,使用表格调度算法实现了任务在RCA上的映射.经过FPGA验证,H.264基准中的核心算法平均执行速度相比于PipeRench,MorphoSys,以及TI DSP TMS320C64X提高了3.34倍.

基于遗传算法的可重构系统软硬件划分

在考虑动态部分重构及重构延时等特征的基础上,采用遗传算法及其与爬山算法的融合实现可重构系统软硬件任务的划分,并采用动态优先级调度算法进行划分结果的评价。实验表明,在可重构系统的资源约束等条件下,算法能够有效地实现应用任务图到可重构系统的时空映射。

遗传算法在软硬件划分中的应用

软硬件划分是软硬协同设计中的一个关键问题。针对单处理器嵌入式系统 ,给出了基于遗传算法的解决方案 ,并引入了模拟退火和按概率选择两种技术。结果表明 ,算法有效地解决了软硬件划分问题 ,稳定性好、效率高 ,模拟退火和按概率选择的引入 ,进一步提高了算法效率 ,保证了算法的自适应性及结果的全局最优性。

基于改进的NSGA遗传算法的SOC软硬件划分方法

在遗传算法中引入精英保持策略构造非支配集和生成新群体,并用排除法构造非支配集,本文得到了一种改进的非支配集分类遗传算法,该算法具有全局收敛特性,并简化了计算复杂性.本文将此算法应用于SOC设计的软硬件划分.针对SOC系统设计中存在多个IP核的特点,采用整数向量的个体编码方案,避免了个体编码解码的冗余.本文给出了仿真实验结果,验证了该划分方法的有效性.

动态可重构技术研究综述

动态可重构技术可使硬件设备在运行时根据不同的计算任务实现不同的功能,在发挥应用程序效率的同时,又能充分利用系统软硬件资源。根据固定器件与可重构器件的关系,可以将可重构系统划分为不同的结构。适应各自结构的特点,将任务合理的分解为软件部分和硬件部分,是高效完成计算任务的基础。当硬件任务较多时,系统需要一个良好的算法来进行调度。最后,可重构系统应该为用户提供一个结构透明的开发平台,使用户可以方便的利用可重构计算的强大能力。

基于遗传和禁忌搜索混合的软硬件划分算法

针对嵌入式系统软硬件划分问题,在比较了遗传算法(GA)和禁忌搜索(TS)各自优缺点的基础上,提出采用遗传/禁忌混合算法(GATS)的策略,用遗传算法提供并行搜索的主框架,用禁忌搜索作为遗传算法的变异算子,遗传算法中变异过程解空间的搜索由禁忌搜索实现。实验结果表明,GATS具有多出发点和记忆功能强、爬山能力强的优势,能够克服GA爬山能力差、TS单点出发的弱点。最后与单纯的遗传算法和禁忌搜索算法进行对比实验,证明GATS更有优势,得到的划分结果也更优秀。

一种有效的面向多目标软硬件划分的遗传算法

软硬件划分是软硬件协同设计的关键技术之一,划分结果对最终的设计方案有非常重要的影响。软硬件划分根据优化目标的数量,可分为单目标划分和多目标划分。多目标划分问题是一个NP-hard问题,一般不存在传统意义上的"最优解",而是存在一组互不支配的Pareto最优解。遗传算法因其具有并行、群体搜索的特点而非常适于求解多目标优化问题。通过抽象描述将一个实际SOC设计问题转化为多目标软硬件划分问题,采用遗传算法便可获得最优设计方案。为克服过早收敛及加快搜索速度,改进了适应度函数的定义,通过自适应参数调整,加入惩罚函数的适应度定义,提高了进化速度,从而有效地获得了Pareto最优解集。在实际问题的应用中,多目标软硬件划分遗传算法是能有效求取平衡系统成本、硬件面积、功耗和时间特性的最优化方案。