Opening the silicon oxide mask of a capacitor in dynamic random access memory is a critical process on a capacitive coupled plasma(CCP)etch tool.Three steps,dielectric anti-reflective coating(DARC)etch back,silicon ox...Opening the silicon oxide mask of a capacitor in dynamic random access memory is a critical process on a capacitive coupled plasma(CCP)etch tool.Three steps,dielectric anti-reflective coating(DARC)etch back,silicon oxide etch and strip,are contained.To acquire good performance,such as low leakage current and high capacitance,for further fabricating capacitors,we should firstly optimize DARC etch back.We developed some experiments,focusing on etch time and chemistry,to evalu-ate the profile of a silicon oxide mask,DARC remain and critical dimension.The result shows that etch back time should be con-trolled in the range from 50 to 60 s,based on the current equipment and condition.It will make B/T ratio higher than 70%mean-while resolve the DARC remain issue.We also found that CH_(2)F_(2) flow should be~15 sccm to avoid reversed CD trend and keep in-line CD.展开更多
DRAM-based memory suffers from increasing row buffer conflicts,which causes significant performance degradation and power consumption.As memory capacity increases,the overheads of the row buffer conflict are increasin...DRAM-based memory suffers from increasing row buffer conflicts,which causes significant performance degradation and power consumption.As memory capacity increases,the overheads of the row buffer conflict are increasingly worse as increasing bitline length,which results in high row activation and precharge latencies.In this work,we propose a practical approach called Row Buffer Cache(RBC)to mitigate row buffer conflict overheads efficiently.At the core of our proposed RBC architecture,the rows with good spatial locality are cached and protected,which are exempted from being interrupted by the accesses for rows with poor locality.Such an RBC architecture significantly reduces the overheads of performance and energy caused by row activation and precharge,and thus improves overall system performance and energy efficiency.We evaluate RBC architecture using SPEC CPU2006 on a DDR4 memory compared to a commodity baseline memory system.Results show that RBC improves the overall performance by up to 2:24(16:1%on average)and reduces the memory energy by up to 68:2%(23:6%on average)for single-core simulations.For multi-core simulations,RBC increases the overall performance by up to1:55(17%on average)and reduces memory energy consumption by up to 35:4%(21:3%on average).展开更多
文摘Opening the silicon oxide mask of a capacitor in dynamic random access memory is a critical process on a capacitive coupled plasma(CCP)etch tool.Three steps,dielectric anti-reflective coating(DARC)etch back,silicon oxide etch and strip,are contained.To acquire good performance,such as low leakage current and high capacitance,for further fabricating capacitors,we should firstly optimize DARC etch back.We developed some experiments,focusing on etch time and chemistry,to evalu-ate the profile of a silicon oxide mask,DARC remain and critical dimension.The result shows that etch back time should be con-trolled in the range from 50 to 60 s,based on the current equipment and condition.It will make B/T ratio higher than 70%mean-while resolve the DARC remain issue.We also found that CH_(2)F_(2) flow should be~15 sccm to avoid reversed CD trend and keep in-line CD.
基金supported by the US National Science Foundation(Nos.CCF-1717660 and CNS-1828363)。
文摘DRAM-based memory suffers from increasing row buffer conflicts,which causes significant performance degradation and power consumption.As memory capacity increases,the overheads of the row buffer conflict are increasingly worse as increasing bitline length,which results in high row activation and precharge latencies.In this work,we propose a practical approach called Row Buffer Cache(RBC)to mitigate row buffer conflict overheads efficiently.At the core of our proposed RBC architecture,the rows with good spatial locality are cached and protected,which are exempted from being interrupted by the accesses for rows with poor locality.Such an RBC architecture significantly reduces the overheads of performance and energy caused by row activation and precharge,and thus improves overall system performance and energy efficiency.We evaluate RBC architecture using SPEC CPU2006 on a DDR4 memory compared to a commodity baseline memory system.Results show that RBC improves the overall performance by up to 2:24(16:1%on average)and reduces the memory energy by up to 68:2%(23:6%on average)for single-core simulations.For multi-core simulations,RBC increases the overall performance by up to1:55(17%on average)and reduces memory energy consumption by up to 35:4%(21:3%on average).
