随着大数据应用的涌现,计算机系统需要更大容量的内存以满足大数据处理的高时效性需求.新型非易失性存储器(non-volatile memory,NVM)结合传统动态随机存储器(dynamic random access memory,DRAM)组成的混合内存系统具有内存容量大、功...随着大数据应用的涌现,计算机系统需要更大容量的内存以满足大数据处理的高时效性需求.新型非易失性存储器(non-volatile memory,NVM)结合传统动态随机存储器(dynamic random access memory,DRAM)组成的混合内存系统具有内存容量大、功耗低的优势,因而得到了广泛关注.大数据应用同时也面临着旁路转换缓冲器(translation lookaside buffer,TLB)缺失率过高的性能瓶颈.大页可以有效降低TLB缺失率,然而,在混合内存中支持大页面临着大页迁移开销过大的问题.因此,设计了一种支持大页和大容量缓存的层次化混合内存系统:DRAM和NVM分别使用4KB和2MB粒度的页面分别进行管理,同时在DRAM和NVM之间实现直接映射.设计了基于访存频率的DRAM缓存数据过滤机制,减轻了带宽压力.提出了基于内存实时信息的动态热度阈值调整策略,灵活适应应用访存特征的变化.实验显示:与使用大页的全NVM内存系统和缓存热页(caching hot page,CHOP)系统相比平均有69.9%和15.2%的性能提升,而与使用大页的全DRAM内存系统相比平均只有8.8%的性能差距.展开更多
Opening the silicon oxide mask of a capacitor in dynamic random access memory is a critical process on a capacitive coupled plasma(CCP)etch tool.Three steps,dielectric anti-reflective coating(DARC)etch back,silicon ox...Opening the silicon oxide mask of a capacitor in dynamic random access memory is a critical process on a capacitive coupled plasma(CCP)etch tool.Three steps,dielectric anti-reflective coating(DARC)etch back,silicon oxide etch and strip,are contained.To acquire good performance,such as low leakage current and high capacitance,for further fabricating capacitors,we should firstly optimize DARC etch back.We developed some experiments,focusing on etch time and chemistry,to evalu-ate the profile of a silicon oxide mask,DARC remain and critical dimension.The result shows that etch back time should be con-trolled in the range from 50 to 60 s,based on the current equipment and condition.It will make B/T ratio higher than 70%mean-while resolve the DARC remain issue.We also found that CH_(2)F_(2) flow should be~15 sccm to avoid reversed CD trend and keep in-line CD.展开更多
半导体技术快速发展,双倍数据速率同步动态随机存取存储器(Double Data Rata Synchronous Dynamic Random Access Memory,DDR SDRAM)的信号完整性问题已成为设计难点。文中提出了一种基于ANSYS软件和IBIS 5.0模型的DDR4 SDRAM信号完整...半导体技术快速发展,双倍数据速率同步动态随机存取存储器(Double Data Rata Synchronous Dynamic Random Access Memory,DDR SDRAM)的信号完整性问题已成为设计难点。文中提出了一种基于ANSYS软件和IBIS 5.0模型的DDR4 SDRAM信号完整性仿真方法。利用IBIS 5.0模型中增加的复合电流(Composite Current)、同步开关输出电流等数据,对DDR4 SDRAM高速电路板的信号完整性进行更准确的仿真分析。仿真结果表明:高速信号在经过印制板走线和器件封装后,信号摆幅和眼图都有明显恶化;在仿真电路的电源上增加去耦电容后,信号抖动和收发端同步开关噪声(Synchronous Switching Noise,SSN)都得到明显改善;在不加去耦电容的情况下,将输入信号由PRBS码换成DBI信号,接收端的同步开关噪声有所改善,器件功耗可以降为原来的一半。展开更多
文摘随着大数据应用的涌现,计算机系统需要更大容量的内存以满足大数据处理的高时效性需求.新型非易失性存储器(non-volatile memory,NVM)结合传统动态随机存储器(dynamic random access memory,DRAM)组成的混合内存系统具有内存容量大、功耗低的优势,因而得到了广泛关注.大数据应用同时也面临着旁路转换缓冲器(translation lookaside buffer,TLB)缺失率过高的性能瓶颈.大页可以有效降低TLB缺失率,然而,在混合内存中支持大页面临着大页迁移开销过大的问题.因此,设计了一种支持大页和大容量缓存的层次化混合内存系统:DRAM和NVM分别使用4KB和2MB粒度的页面分别进行管理,同时在DRAM和NVM之间实现直接映射.设计了基于访存频率的DRAM缓存数据过滤机制,减轻了带宽压力.提出了基于内存实时信息的动态热度阈值调整策略,灵活适应应用访存特征的变化.实验显示:与使用大页的全NVM内存系统和缓存热页(caching hot page,CHOP)系统相比平均有69.9%和15.2%的性能提升,而与使用大页的全DRAM内存系统相比平均只有8.8%的性能差距.
文摘Opening the silicon oxide mask of a capacitor in dynamic random access memory is a critical process on a capacitive coupled plasma(CCP)etch tool.Three steps,dielectric anti-reflective coating(DARC)etch back,silicon oxide etch and strip,are contained.To acquire good performance,such as low leakage current and high capacitance,for further fabricating capacitors,we should firstly optimize DARC etch back.We developed some experiments,focusing on etch time and chemistry,to evalu-ate the profile of a silicon oxide mask,DARC remain and critical dimension.The result shows that etch back time should be con-trolled in the range from 50 to 60 s,based on the current equipment and condition.It will make B/T ratio higher than 70%mean-while resolve the DARC remain issue.We also found that CH_(2)F_(2) flow should be~15 sccm to avoid reversed CD trend and keep in-line CD.
