A 1 ： 2 demultiplexer（DEMUX） that is fabricated using 0. 18 μm CMOS （complementary metaloxide-semiconductor transistor） technology is presented. The DEMUX consists of a master-slave-slave, masterslave D flip-flo...A 1 ： 2 demultiplexer（DEMUX） that is fabricated using 0. 18 μm CMOS （complementary metaloxide-semiconductor transistor） technology is presented. The DEMUX consists of a master-slave-slave, masterslave D flip-flops and output buffers. The D flip-flop employs a dynamic-loading structure and common-gate topology with single clock phase for the bias transistors. The dynamic-loading structure can make the circuit work faster because it decreases the charge/discharge time of the output node, and it consumes lower power because its working current is in a switch mode. In addition, the positive feedback loop, which is made up of a cross-coupled transistor pair in the latch, speeds up the circuit. Measurement results at 20 Gbit/s 2^23 - 1 pseudo random bit sequence （PRBS） via on-wafer testing show that the 1： 2 DEMUX can operate well. The power dissipation is 108 mW with the area of 475μm×578μm.展开更多
This paper presents the design and analysis of a high speed broadband divide-by-2 frequency divider. The proposed divider is a dynamic source-coupled logic（DSCL） structure formed with two dynamic-loading master-slav...This paper presents the design and analysis of a high speed broadband divide-by-2 frequency divider. The proposed divider is a dynamic source-coupled logic（DSCL） structure formed with two dynamic-loading master-slave D latches,which enables high frequency operation and low power consumption.This divider exhibits a wide locking range from 7-27 GHz and the minimum power consumption is only 1.22 mW from a 1.2 V supply.The input sensitivity is as low as -25.4 dBm across the operating frequency range.This chip occupies 685×430μm^2 area with two on-chip spiral inductors in 90 nm CMOS process.展开更多
文摘A 1 ： 2 demultiplexer（DEMUX） that is fabricated using 0. 18 μm CMOS （complementary metaloxide-semiconductor transistor） technology is presented. The DEMUX consists of a master-slave-slave, masterslave D flip-flops and output buffers. The D flip-flop employs a dynamic-loading structure and common-gate topology with single clock phase for the bias transistors. The dynamic-loading structure can make the circuit work faster because it decreases the charge/discharge time of the output node, and it consumes lower power because its working current is in a switch mode. In addition, the positive feedback loop, which is made up of a cross-coupled transistor pair in the latch, speeds up the circuit. Measurement results at 20 Gbit/s 2^23 - 1 pseudo random bit sequence （PRBS） via on-wafer testing show that the 1： 2 DEMUX can operate well. The power dissipation is 108 mW with the area of 475μm×578μm.
基金supported by the National Basic Research Program of China(No.2010CB327404)the National Natural Science Foundation of China(No.60901012)
文摘This paper presents the design and analysis of a high speed broadband divide-by-2 frequency divider. The proposed divider is a dynamic source-coupled logic（DSCL） structure formed with two dynamic-loading master-slave D latches,which enables high frequency operation and low power consumption.This divider exhibits a wide locking range from 7-27 GHz and the minimum power consumption is only 1.22 mW from a 1.2 V supply.The input sensitivity is as low as -25.4 dBm across the operating frequency range.This chip occupies 685×430μm^2 area with two on-chip spiral inductors in 90 nm CMOS process.
