A Static Phase Offset Reduction Technique for Multiplying Delay-Locked Loop

Static phase offset (SPO) in conventional multiplying delay-locked loops (MDLLs) dramatically degrades the deterministic jitter performance. To overcome the issue, this paper presents a new SPO reduction technique for MDLLs. The technique is based on the observation that the SPO of MDLL is mainly caused by the non-idealities on charge pump (e.g. sink and source current mismatch), and control line (e.g. gate leakage of loop filter and voltage controlled delay line (VCDL) control circuit). With a high gain stage inserting between phase detector/phase frequency detector (PD/PFD) and charge pump, the equivalent SPO has been decreased by a factor equal to the gain of the gain stage. The effectiveness of the proposed technique is validated by a Simulink model of MDLL. The equivalent SPO is measured by the power level of reference spur.

Method to Improve the Tracking Speed of the Early-Late Synchronizer

A new early-late synchronizer is proposed to improve tracking speed. The performance of the traditional early-late synchronizer is analyzed in detail, the result shows that the different location and length of integral period can influence the discriminator characteristic, an improved integral structure is provided which can tracking the synchronization error better. According to the good tracking performance of Kalman filter, a new loop filter is designed. The new early-late synchronizer adopts both the new integral structure and the new loop filter. The analysis with loop theory and simulation results in Simulink show that the new bit synchronizer possesses higher tracking speed than the traditional early-late synchronizer.

Error Correction Circuit for Single-Event Hardening of Delay Locked Loops

In scaled CMOS processes, the single-event effects generate missing output pulses in Delay-Locked Loop (DLL). Due to its effective sequence detection of the missing pulses in the proposed Error Correction Circuit (ECC) and its portability to be applied to any DLL type, the ECC mitigates the impact of single-event effects and completes its operation with less design complexity without any concern about losing the information. The ECC has been implemented in 180 nm CMOS process and measured the accuracy of mitigation on simulations at LETs up to 100 MeV-cm2/mg. The robustness and portability of the mitigation technique are validated through the results obtained by implementing proposed ECC in XilinxArtix 7 FPGA.

Multipath mitigation method for tracking Galileo signals

In order to improve the performance of multipath mitigation in tracking Galileo signals, a new multipath mitigation method named early-late strobe correlator （ELSC） is proposed. By applying the strobe correlator used widely in global positioning system （GPS） scenarios to Galileo E1 signals, it can be found that the strobe correlator has an undesirable level of performance when the delay of multipath signals is about 0. 5 chip. Combining several strobe correlators, the ELSC can effectively mitigate the multipath effect especially for the multipath signals with the 0. 5 chip delay. The multipath error envelopes between the strobe correlator and the ELSC are compared for Galileo E1 signals. The simulation results indicate that the ELSC performs excellently on multipath mitigation, and can be applied in both Galileo scenarios and GPS scenarios.

Novel Joint Chip Sampling and Phase Synchronization Algorithm for Multistandard UMTS Systems

CDMA Timing and phase offsets tracking remain as one of considerable factors that influence the performances of communication systems. Many algorithms are proposed to solve this problem. In general, these solutions process separately the chip sampling offset and phase rotation. In addition, most of proposed solutions can not assure a compromise between robustness criteria and low complexity for implementation in real time applications. In this paper we present an efficient algorithm for chip sampling and phase synchronization. This algorithm allows estimating and correcting jointly in real time, sampling instant and phase errors. The robustness and the low complexity of this algorithm are evaluated, firstly by simulation and then tested by real experimentation for UMTS standard. Simulation results show that the proposed algorithm provides very efficient compensation for sampling clock offset and phase rotation. A real time implementation is achieved, based on TigerSharc DSP, while using a complete UMTS transmission-reception chain. Experimental results show robustness in real conditions.