Design and implementation of instruction-driven and data-driven self-reconfigurable cell array

The reconfigurable chip,which integrates the advantages of high performance,high flexibility,high parallelism,low power consumption,and low cost,has achieved rapid development and wide application.Generally,the control part and the computing part of algorithm is accelerated based on different reconfigurable architectures,but it is difficult to obtain overall performance improvement.For improving efficiency of reconfigurable structure both for the control part and the computing part,a hybrid of instruction-driven and data-driven self-reconfigurable cell array is proposed.On instruction-driven mode,processing element(PE)works like a reduced instruction set computer(RSIC)machine,which is mainly for the control part of algorithm.On data-driven mode,data is calculated by flowing between the preconfigured PEs,which is mainly for the computing of algorithm.For verifying the efficiency of architecture,some high-efficiency video coding(HEVC)video compression algorithms are implemented on the proposed architecture.The proposed architecture has been implemented on Xilinx FPGA Virtex UltraScale VU440 develop board.The same circuitry is able to run at75 MHz.Compared with the architecture that only supports instruction-driven,the proposed architecture has better calculation efficiency.

High-Bandwidth,Low-Power CMOS Transistor Based CAB for Field Programmable Analog Array

This article presents an integrated current mode configurable analog block(CAB)system for field-programmable analog array(FPAA).The proposed architecture is based on the complementary metal-oxide semiconductor(CMOS)transistor level design where MOSFET transistors operating in the saturation region are adopted.The proposed CAB architecture is designed to implement six of thewidely used current mode operations in analog processing systems:addition,subtraction,integration,multiplication,division,and pass operation.The functionality of the proposed CAB is demonstrated through these six operations,where each operation is chosen based on the user’s selection in the CAB interface system.The architecture of the CAB system proposes an optimized way of designing and integrating only three functional cells with the interface circuitry to achieve the six operations.Furthermore,optimized programming and digital tuning circuitry are implemented in the architecture to control and interface with the functional cells.Moreover,these designed programming and tuning circuitries play an essential role in optimizing the performance of the proposed design.Simulation of the proposed CMOS Transistor Based CAB system is carried out using Tanner EDA Tools in 0.35μm standard CMOS technology.The design uses a±1.5 V power supply and results in maximum 3 dB bandwidth of 34.9 MHz and an approximate size of 0.0537 mm2.This demonstrates the advantages of the design over the current state-of-the-art designs presented for comparison in this article.Consequently,the proposed design has a clear aspect of simplicity,low power consumption,and high bandwidth operation,which makes it a suitable candidate for mobile telecommunications applications.

Evaluation of series-parallel-cross-tied PV array configuration performance with maximum power point tracking techniques under partial shading conditions

Tracking the maximum power point is a critical issue with solar systems.The power output of the solar panel varies due to variations in irradiance and temperature.Nonuniform irradiation due to partial shading conditions has a direct impact on the characteristics of photovoltaic(PV)systems.To build a diversity of maximum power point tracking algorithms in solar PV systems,this work focuses on perturb and observe,incremental conductance,and fuzzy logic control methodologies.The suggested fuzzy logic control method outperformed the conventional incremental conductance and perturb and observe algorithms with a collection of 49 rules.This paper presents a novel series-parallel-cross-tied PV array configuration with a developed fuzzy methodology.To comment on the performance of a proposed system under various partial shading conditions,a series-parallel PV array configuration has been considered.The simulation result demonstrates that the fuzzy method has a percentage improvement in the global maximum power point tracking efficiency of 24.85%when compared to the perturb and observe method and a 65.5%improvement when compared to the incremental conductance method under long wide partial shading conditions.In the case of the middle partial shading condition,the fuzzy method has a percentage improvement in the global maximum power point tracking efficiency of 12.4%compared to the perturb and observe method and a 60.7%improvement compared to the incremental conductance method.

GERO: a general SCA-based readout ASIC for micro-pattern gas detectors with configurable storage depth and on-chip digitizer

The paper presents GEneral ReadOut (GERO), a general readout ASIC based on a switched capacitor array for micro-pattern gas detectors. It aims at providing general readout electronics for low-to-medium event-rate gas detectors with high sampling frequency, configurable storage depth, and data digitalization. The first prototype GERO chip integrates 16 channels and was fabricated using a 0.18-lm CMOS process. Each channel consists of a sampling array working in a ping-pong mode, a storage array with a 1024-cell depth, and 32 Wilkinson analog-todigital converters. The detailed design and test results are presented in the paper.

MIXED-GRAINED CMOS FIELD PROGRAMMABLE ANALOG ARRAY FOR SMART SENSORY APPLICATIONS

The drive towards shorter design cycles for analog integrated circuits has given impetus to the development of Field Programmable Analog Arrays(FPAAs),which are the analogue counterparts of Field Programmable Gate Arrays(FPGAs).In this paper,we present a new design methodology which using FPAA as a powerful analog front-end processing platform in the smart sensory microsystem.The proposed FPAA contains 16 homogeneous mixed-grained Configurable Analog Blocks(CABs) which house a variety of processing elements especially the proposed fine-grained Core Configurable Amplifiers(CCAs).The high flexible CABs allow the FPAA operating in both continuous-time and discrete-time approaches suitable to support variety of sensors.To reduce the nonideal parasitic effects and save area,the fat-tree interconnection network is adopted in this FPAA.The functionality of this FPAA is demonstrated through embedding of voltage and capacitive sensor signal readout circuits and a configurable band pass filter.The minimal detectable voltage and capacitor achieves 38 uV and 8.3 aF respectively within 100 Hz sensor bandwidth.The power consumption comparison of CCA in three applications shows that the FPAA has high power efficiency.And the simulation results also show that the FPAA has good tolerance with wide PVT variations.

A Novel Triple-tied-cross-linked PV Array Configuration with Reduced Number of Cross-ties to Extract Maximum Power Under Partial Shading Conditions

Partial shadings cause output power reduction from Photovoltaic(PV)arrays due to mismatch losses.The selection of PV array configurations play a vital role in maximum power generation.This paper proposes a novel Triple-Tied-Cross-Linked(T-T-C-L)configuration to extract maximum power with a lesser number of cross ties than a Total-Cross-Tied(T-C-T)configuration.The performance of the proposed T-T-C-L configuration has been compared with various conventional PV array configurations,such as Series(S),Parallel(P),Series-Parallel(S-P),Bridge-Link(B-L),Honey-Comb(H-C),and T-C-T under Partial Shading Conditions(PSCs)by considering the 9×9 PV array.The PSCs considered are uneven row,column,diagonal,random,short&narrow,short&wide,long&narrow,long&wide shadings and uniform half module shading.The measures,such as open circuit voltage,short circuit current,maximum power,voltages and currents at maximum power,mismatch losses,fill factor and efficiency have been used for performance analysis of various configurations.From the results,it can be concluded that the performance of the proposed T-T-C-L configuration is optimal compared to other configurations.

Optimal PV Array Configuration for Extracting Maximum Power Under Partial Shading Conditions by Mitigating Mismatching Power Losses

The grid-connected or standalone PV central inverter architecture is comprised of several PV modules which are connected in different ways to form the PV array.The power generation capability of the PV array is primarily affected by partial shading conditions(PSC).Due to PSCs,the power output of the PV array is dramatically reduced,and mismatching losses are induced in the PV modules.Based on the extent of these problems,multiple peaks also appear in the power-voltage(P-V)curve,which makes it very difficult to track the global maximum power point(GMPP).The main objective of this research paper is to model and simulate the series(S),series-parallel(SP),bridge-link(BL),honey-comb(HC),total-cross-tied(TCT)and proposed triple-tied(TT)solar PV array configurations under various partial shading scenarios.The performance of all PV configurations is evaluated under a uniform approach,considering eight different shading scenarios.The performance of the considered PV configurations is analyzed in terms of their mismatching power losses,fill factors,efficiency,global maximum power points(GMPPs),local maximum power points(LMPPs),voltages and currents at GMPPs,open circuit voltage and short circuit currents.The above-mentioned PV configurations are modeled and simulated in a Matlab/Simulink environment by considering the KC-200GT module parameters.

Performance Investigation of Hybrid and Conventional PV Array Configurations for Grid-connected/Standalone PV Systems

Currently,the critical challenge in solar photovoltaic(PV)systems is to make them energy efficient.One of the key factors that can reduce the PV system power output is partial shading conditions(PSCs).The reduction in power output not only depends on a shaded region but also depends on the pattern of shading and physical position of shaded modules in the array.Due to PSCs,mismatch losses are induced between the shaded modules which can cause several peaks in the output power-voltage(P-V)characteristics.The series-parallel(SP),total-cross-tied(TCT),bridge-link(BL),honey-comb(HC),and triple-tied(TT)configurations are considered as conventional configurations,which are severely affected by PSCs and generate more mismatch power losses along with a greater number of local peaks.To reduce the effect of PSCs,hybrid PV array configurations,such as series-parallel:total-cross-tied(SP-TCT),bridge-link:total-cross-tied(BL-TCT),honey-comb:total-cross-tied(HC-TCT)and bridge-link:honey-comb(BL-HC)are proposed.This paper briefly discusses the modeling,simulation and performance evaluation of hybrid and conventional 7×7 PV array configurations during different PSCs in a Matlab/Simulink environment.The performance of hybrid and conventional PV configurations are evaluated and compared in terms of global maximum power(GMP),voltage and currents at GMP,open and short circuit voltage and currents,mismatch power loss(MPL),fill factor,efficiency,and a number of local maximum power peaks(LMPPs).

Analyses of edge plasma characteristics in HL-2A

The edge plasma characteristics are studied by both a movable array of Much/Reynolds stress/Langmuir 10-probes in the boundary region and the fixed flush probe arrays on the 4 divertor neutralization plates at the same toroidal crosssection in the HL-2A tokamak. The dependence of the Reynolds stress on poloidal flow in the edge plasma is analysed. The result indicates that the sheared poloidal flow in tokamak plasma can be induced by the radial gradient of Reynolds stress. In the divertor experiments of HL-2A, the profiles of the electron temperature, density and floating potential on divertor plates are measured by the flush probe arrays. The edge electron temperature in divertor configuration is higher than that in limiter configuration. The temperature asymmetry between outer and inner target plates is observed. The result of magnetic surface reconstructed from 18 Mirnov coils signals is presented. Both the particle recycling and the impurity flux in the bulk plasma during divertor discharges are discussed. Neutral gas pressure in divertor chamber, measured by fast ionization gauge during divertor discharge, is given.

Dynamical Self-Reconfigurable Mechanism for Data-Driven Cell Array

The utilization of computation resources and reconfiguration time has a large impact on reconfiguration system performance. In order to promote the performance, a dynamical self-reconfigurable mechanism for data-driven cell array is proposed. Cells can be fired only when the needed data arrives, and cell array can be worked on two modes: fixed execution and reconfiguration. On reconfiguration mode, cell function and data flow direction are changed automatically at run time according to contexts. Simultaneously using an H-tree interconnection network, through pre-storing multiple application mapping contexts in reconfiguration buffer, multiple applications can execute concurrently and context switching time is the minimal. For verifying system performance, some algorithms are selected for mapping onto the proposed structure, and the amount of configuration contexts and execution time are recorded for statistical analysis. The results show that the proposed self-reconfigurable mechanism can reduce the number of contexts efficiently, and has a low computing time.

Practical configured microtremor array measurements(MAMs)for the geological investigation of underground space

Underground space utilization is becoming increasingly essential for modern metropolitan cities such as Singapore.Mapping a soil/rock interface using traditional borehole investigation methods is expensive and difficult,owing to the numerous physical constraints within a built-up city.Boreholes are often far apart,resulting in many unforeseen ground conditions during subsequent excavation.Geophysical methods are sometimes employed as possible alternatives for fast,economical,and efficient bedrock surveys.The goal of this study is to investigate the practical details of applying microtremor array measurement(MAM)as a non-invasive surface wave survey for mapping soil/rock interfaces in Singapore.Critical configurations in field data acquisition are examined,and practical recommendations for array construction are provided.In addition,30 in situ MAM tests are carried out for two major geological formations in Singapore.From the results,a standard shear wave velocity(V_(s))of 500 m/s is found to be suitable for interpreting the soil/rock interface,for the Bukit Timah Granite and Jurong formations.However,the method does not predict well when soft Kallang formation deposits are present.Other limitations are also discussed in the later parts of this paper.Conclusions and practical recommendations are discussed,providing constructive guidance to the industry.The proposed Vs-based method and associated guidelines and limitations can be used to create a digital geological database and are especially useful for rock profiling in an urban environment.

A HW/SW Co-Verification Technique for FPGA Test

Field programmable gate arrays （FPGAs） have wide and extensive applications in many areas. Due to programmable feature of FPGAs, faults of FPGAs can be easily tolerated if fault sites can be located. A hardware/software （HW/SW） co-verification technique for FPGA test is proposed in this paper. Taking advantage of flexibility and observability of software in conjunction with high-speed simulation of hardware, this technique is capable of testing each input/output block （IOB） and configurable logic block （CLB） of FPGA automatically, exhaustively and repeatedly. Fault cells of FPGA can be positioned automatically by the proposed approach. As a result, test efficiency and reliability can be enhanced without manual work.

Optimal Su-Do-Ku based interconnection scheme for increased power output from PV array under partial shading conditions

Partial shading is a common phenomenon in PV arrays. They drastically reduce the power output because of mismatch losses, which are reliant on the shape of the shade as well as the locations of shaded panels in the array. The power output can be improved by distributing the shade over various rows to maximize the current entering the node. A Su-Do-Ku configuration can be used to rearrange the physical locations of the PV modules in a total cross tied PV array with the electrical connections left unchanged. However, this arrangement increases the length of the wire required to interconnect the panels thus increasing the line losses. In this paper, an improved Su-Do-Ku arrangement that reduces the length of the wire required for the connection is proposed. The system is designed and simulated in a Matlab/Simulink environment for various shading patterns and the efficacies of various arrangements are compared. The results prove that the power output is higher in the proposed improved Su-Do- Ku reconfiguration technique compared to the earlier proposed Su-Do-Ku technique.

Design and analysis of a dual mode CMOS field programmable analog array

This paper presents a novel field-programmable analog array （FPAA） architecture featuring a dual mode including discrete-time （DT） and continuous-time （CT） operation modes, along with a highly routable connection boxes （CBs） based interconnection lattice. The dual mode circuit for the FPAA is capable of achieving targeted op- timal performance in different applications. The architecture utilizes routing switches in a CB not only for the signal interconnection purpose but also for control of the electrical charge transfer required in switched-capacitor circuits. This way, the performance of the circuit in either mode shall not be hampered with adding of programmability. The proposed FPAA is designed and implemented in a 0.18 μm standard CMOS process with a 3.3 V supply voltage. The result from post-layout simulation shows that a maximum bandwidth of 265 MHz through the interconnection network is achieved. The measured results from demonstrated examples show that the maximum signal bandwidth of up to 2 MHz in CT mode is obtained with the spurious free dynamic range of 54 dB, while the signal processing precision in DT mode reaches 96.4%.