Enhancement of holding voltage by a modified low-voltage trigger silicon-controlled rectifier structure for electrostatic discharge protection

A novel structure of low-voltage trigger silicon-controlled rectifiers(LVTSCRs) with low trigger voltage and high holding voltage is proposed for electrostatic discharge(ESD) protection. The proposed ESD protection device possesses an ESD implant and a floating structure. This improvement enhances the current discharge capability of the gate-grounded NMOS and weakens the current gain of the silicon-controlled rectifier current path. According to the simulation results, the proposed device retains a low trigger voltage characteristic of LVTSCRs and simultaneously increases the holding voltage to 5.53 V, providing an effective way to meet the ESD protection requirement of the 5 V CMOS process.

A novel diode string triggered gated-Pi N junction device for electrostatic discharge protection in 65-nm CMOS technology

A novel diode string-triggered gated-Pi N junction device, which is fabricated in a standard 65-nm complementary metal-oxide semiconductor（CMOS） technology, is proposed in this paper. An embedded gated-Pi N junction structure is employed to reduce the diode string leakage current to 13 n A/μm in a temperature range from 25°C to 85°C. To provide the effective electrostatic discharge（ESD） protection in multi-voltage power supply, the triggering voltage of the novel device can be adjusted through redistributing parasitic resistance instead of changing the stacked diode number.

Structure-dependent behaviors of diode-triggered silicon controlled rectifier under electrostatic discharge stress

The comprehensive understanding of the structure-dependent electrostatic discharge behaviors in a conventional diode-triggered silicon controlled rectifier （DTSCR） is presented in this paper. Combined with the device simulation, a mathematical model is built to get a more in-depth insight into this phenomenon. The theoretical studies are verified by the transmission-line-pulsing （TLP） test results of the modified DTSCR structure, which is realized in a 65-nm complementary metal-oxide-semiconductor （CMOS） process. The detailed analysis of the physical mechanism is used to provide predictions as the DTSCR-based protection scheme is required. In addition, a method is also presented to achieve the tradeoff between the leakage and trigger voltage in DTSCR.

High holding voltage SCR for robust electrostatic discharge protection

A novel silicon controlled rectifier（SCR） with high holding voltage（Vh） for electrostatic discharge（ESD） protection is proposed and investigated in this paper. The proposed SCR obtains high Vhby adding a long N＋ layer（LN＋） and a long P＋ layer（LP＋）, which divide the conventional low voltage trigger silicon controlled rectifier（LVTSCR） into two SCRs（SCR1： P＋/Nwell/Pwell/N＋ and SCR2： P＋/LN＋/LP＋/N＋） with a shared emitter. Under the low ESD current（IESD）, the two SCRs are turned on at the same time to induce the first snapback with high V_h（V_（h1））. As the IESDincreases, the SCR2 will be turned off because of its low current gain. Therefore, the IESDwill flow through the longer SCR1 path, bypassing SCR2, which induces the second snapback with high V_h（V_（h2））. The anti-latch-up ability of the proposed SCR for ESD protection is proved by a dynamic TLP-like（Transmission Line Pulse-like） simulation. An optimized V_（h2） of 7.4 V with a maximum failure current（I_（t2）） of 14.7 m A/μm is obtained by the simulation.

Enhanced gated-diode-triggered silicon-controlled rectifier for robust electrostatic discharge (ESD) protection applications

A robust electron device called the enhanced gated-diode-triggered silicon-controlled rectifier (EGDTSCR) for electrostatic discharge (ESD) protection applications has been proposed and implemented in a 0.18-μm 5-V/24-V BCD process. The proposed EGDTSCR is constructed by adding two gated diodes into a conventional ESD device called the modified lateral silicon-controlled rectifier (MLSCR). With the shunting effect of the surface gated diode path, the proposed EGDTSCR, with a width of 50 μm, exhibits a higher failure current (i.e., 3.82 A) as well as a higher holding voltage (i.e., 10.21 V) than the MLSCR.

Study on electrostatic discharge(ESD)characteristics of ultra-thin dielectric film

Electrostatic discharge(ESD)event usually destroys the electrical properties of dielectric films,resulting in product failure.In this work,the breakdown characteristic of machine mode(MM)ESD on three different nano size films of head gimble assemble are obtained experimentally.The breakdown voltage and thickness parameters show a positive proportional relationship,but they are generally very low and have large discrete characteristics(~30%).The maximum and minimum breakdown voltages of the tested samples are 1.08 V and 0.46 V,which are far lower than the requirement of the current standard(25 V).In addition,the judgment criterion of product damage is given,and the relationship between discharge voltage polarity,initial resistance and breakdown voltage is studied.Finally,the theoretical analysis of the breakdown characteristic law has been given.

Dynamic electrostatic-discharge path investigation relied on different impact energies in metal-oxide-semiconductor circuits

Gate-grounded n-channel metal-oxide-semiconductor(GGNMOS)devices have been widely implemented as power clamps to protect semiconductor devices from electrostatic discharge stress owing to their simple construction,easy triggering,and low power dissipation.We present a novel I-V characterization of the GGNMOS used as the power clamp in complementary metal-oxide-semiconductor circuits as a result of switching the ESD paths under different impact energies.This special effect could cause an unexpected latch-up or pre-failure phenomenon in some applications with relatively large capacitances from power supply to power ground,and thus should be urgently analyzed and resolved.Transmission-linepulse,human-body-modal,and light-emission tests were performed to explore the root cause.

The abnormal electrostatic discharge of a no-connect metal cover in a ceramic packaging device

The human body model（HBM） stress of a no-connect metal cover is tested to obtain the characteristics of abnormal electrostatic discharge,including current waveforms and peak current under varied stress voltage and device failure voltage.A new discharge model called the ＂sparkover-induced model＂ is proposed based on the results.Then,failure mechanism analysis and model simulation are performed to prove that the transient peak current caused by a sparkover of low arc impedance will result in the devices＇ premature damage when the potential difference between the no-connect metal cover and the chip exceeds the threshold voltage of sparkover.

An improved GGNMOS triggered SCR for high holding voltage ESD protection applications

Developing an electrostatic discharge（ESD） protection device with a better latch-up immunity has been a challenging issue for the nanometer complementary metal-oxide semiconductor（CMOS） technology. In this work, an improved grounded-gate N-channel metal-oxide semiconductor（GGNMOS） transistor triggered silicon-controlled rectifier（SCR）structure, named GGSCR, is proposed for high holding voltage ESD protection applications. The GGSCR demonstrates a double snapback behavior as a result of progressive trigger-on of the GGNMOS and SCR. The double snapback makes the holding voltage increase from 3.43 V to 6.25 V as compared with the conventional low-voltage SCR. The TCAD simulations are carried out to verify the modes of operation of the device.

Novel substrate trigger SCR-LDMOS stacking structure for high-voltage ESD protection application

A novel substrate trigger semiconductor control rectifier-laterally diffused metal-oxide semiconductor （STSCR- LDMOS） stacked structure is proposed and simulated using the transimission line pulser （TLP） multiple-pulse simulation method in a 0.35μm, 60-V biploar-CMOS-DMOS （BCD） process without additional masks. On account of a very low holding voltage, it is susceptible to latch-up-like danger for the semiconductor control rectifier-laterally diffused metaloxide semiconductor （SCR-LDMOS） in high-voltage electro-static discharge （ESD） protection applications. Although the conventional stacking structure has achieved strong latch-up immunity by increasing holding voltage, excessive high trigger voltage does not meet requirements for an ESD protection device. The holding voltage of the proposed stacked structure is proportional to the stacking number, whereas the trigger voltage remains nearly the same. A high holding voltage of 30.6 V and trigger voltage of 75.4 V are achieved.

Low-parasitic ESD protection strategy for RF ICs in 0.35μm CMOS process

A systemic and comprehensive ESD-induced parasitic model is presented in this paper, which is used to analyse the parasitic influences of electrostatic discharge （ESD） protection circuits on the performance of radio frequency applications. A novel low-parasitic ESD protection structure is made in a 0.35μm 1P3M silicide CMOS process. The measured results show that this novel structure has a low parasitic capacitance about 310fF and a low leakage current about 12.2nA with a suitable ESD robustness target about 5kV human body model.

Design of a novel high holding voltage LVTSCR with embedded clamping diode

In order to reduce the latch-up risk of the traditional low-voltage-triggered silicon controlled rectifier(LVTSCR), a novel LVTSCR with embedded clamping diode(DC-LVTSCR) is proposed and verified in a 0.18-μm CMOS process. By embedding a p+implant region into the drain of NMOS in the traditional LVTSCR, a reversed Zener diode is formed by the p+implant region and the n+bridge, which helps to improve the holding voltage and decrease the snapback region.The physical mechanisms of the LVTSCR and DC-LVTSCR are investigated in detail by transmission line pulse(TLP)tests and TCAD simulations. The TLP test results show that, compared with the traditional LVTSCR, the DC-LVTSCR exhibits a higher holding voltage of 6.2 V due to the embedded clamping diode. By further optimizing a key parameter of the DC-LVTSCR, the holding voltage can be effectively increased to 8.7 V. Therefore, the DC-LVTSCR is a promising ESD protection device for circuits with the operation voltage of 5.5–7 V.

The characteristics of primary and secondary arcs on a solar array in low earth orbit

In this paper, the characteristics of the primary arc and secondary arc on a solar array in low earth orbit（LEO） are investigated. The vacuum plasma environment in LEO has been used to study the primary arc and secondary arc of a high-voltage solar array. Silicon solar cells with rigid substrate specimens are used for the experiment. The series-parallel spacing of the silicon solar cells is 1 mm. The string currents of the solar cells are 0.7 A, 1.5 A and 2 A. The primary arc and secondary arc are photographed by high-speed cameras. The differences between the primary arc and secondary arc are observed. The secondary arc can be observed before the primary arc is extinguished. The primary arc is a single arc when the string current is 0.7 A. Multiple arc columns are accompanied by higher arc current. Two arc columns of the primary arc can be observed at 1.5 A string current and 2 A string current. The multiple primary arc columns are related to higher bias voltage. The threshold for sustained arcing is near 145 V/0.7 A, 105 V/1.5 A and 100 V/2 A at 1 mm string gap. Moreover, the transition time of secondary arc formation is analyzed, and found to be about 10–13 μs. The string currents, string voltages and primary arc have no effect on the transition time of the secondary arc formation.

Terminal-optimized 700-V LDMOS with improved breakdown voltage and ESD robustness

A novel terminal-optimized triple RESURF LDMOS(TOTR-LDMOS) is proposed and verified in a 0.25-μm bipolarCMOS-DMOS(BCD) process. By introducing a low concentration region to the terminal region, the surface electric field of the TOTR-LDMOS decreases, helping to improve the breakdown voltage(BV) and electrostatic discharge(ESD) robustness. Both traditional LDMOS and TOTR-LDMOS are fabricated and investigated by transmission line pulse(TLP) tests,direct current(DC) tests, and TCAD simulations. The results show that comparing with the traditional LDMOS, the BV of the TOTR-LDMOS increases from 755 V to 817 V without affecting the specific on-resistance(R_(on,sp)) of 6.99Ω·mm^(2).Meanwhile, the ESD robustness of the TOTR-LDMOS increases by 147%. The TOTR-LDMOS exhibits an excellent performance among the present 700-V LDMOS devices.

Design and investigation of novel ultra-high-voltage junction field-effect transistor embedded with NPN

Ultra-high-voltage(UHV)junction field-effect transistors(JFETs)embedded separately with the lateral NPN(JFETLNPN),and the lateral and vertical NPN(JFET-LVNPN),are demonstrated experimentally for improving the electrostatic discharge(ESD)robustness.The ESD characteristics show that both JFET-LNPN and JFET-LVNPN can pass the 5.5-k V human body model(HBM)test.The JFETs embedded with different NPNs have 3.75 times stronger in ESD robustness than the conventional JFET.The failure analysis of the devices is performed with scanning electron microscopy,and the obtained delayer images illustrate that the JFETs embedded with NPN transistors have good voltage endurance capabilities.Finally,the internal physical mechanism of the JFETs embedded with different NPNs is investigated with emission microscopy and Sentaurus simulation,and the results confirm that the JFET-LVNPN has stronger ESD robustness than the JFET-LNPN,because the vertical NPN has a better electron collecting capacity.The JFET-LVNPN is helpful in providing a strong ESD protection and functions for a power device.

Evaluation of the Capacitance and Charge Distribution for Conducting Bodies by Circuit Modelling

This paper presents a numerical analysis for computation of free space capacitance of different arbitrarily shaped conducting bodies based on the finite element method with triangular subsection modeling. Evaluation of capacitance of different arbitrary shapes is important for the electrostatic analysis. Capacitance computation is an important step in the prediction of electrostatic discharge which causes electromagnetic interference. We specifically illustrated capacitance computation of electrostatic models like unit cube, rectangular plate, triangular plate, T-shaped plate, sphere and two touching spheres. Numerical data on the capacitance of conducting objects are presented. The results are compared with other available results in the literature. We used the COMSOL Multiphysics software for the simulation. The models are designed in three-dimensional form using electrostatic environment and can be applied to any spacecraft circuit modeling design. The findings of this study show that the finite element method is a more accurate method and can be applied to any circuit modeling design.

The Biological Property of Synthetic Evolved Digital Circuits with ESD Immunity - Redundancy or Degeneracy？

In the ongoing evolutionary process, biological systems have displayed a fundamental and remarkable property of robustness, i.e., the property allows the system to maintain its functions despite external and internal perturbations. Redundancy and degeneracy are thought to be the underlying structural mechanisms of biological robustness. Inspired by this, we explored the proximate cause of the immunity of the synthetic evolved digital circuits to ESD interference and discussed the biological characteristics behind the evolutionary circuits. First, we proposed an evolutionary method for intrinsic immune circuit design. The circuits＇ immunity was evaluated using the functional fault models based on probability distributions. Then, several benchmark circuits, including ADDER, MAJORITY, and C17, were evolved for high intrinsic immunity. Finally, using the quantitative definitions based on information theory, we measured the topological characteristics of redundancy and degeneracy in the evolved circuits and compared their contributions to the immunity. The results show that redundant elements are neces- sary for the ESD immune circuit design, whereas degeneracy is the key to making use of the redundancy robustly and efficiently.

Influence of layout parameters on snapback characteristic for a gate-grounded NMOS device in 0.13-μm silicide CMOS technology

Gate-grounded NMOS （GGNMOS） devices with different device dimensions and layout floorplans have been designed and fabricated in 0.13-μm silicide CMOS technology. The snapback characteristics of these GGN-MOS devices are measured using the transmission line pulsing （TLP） measurement technique. The relationships between snapback parameters and layout parameters are shown and analyzed. A TCAD device simulator is used to explain these relationships. From these results, the circuit designer can predict the behavior of the GGNMOS devices under high ESD current stress, and design area-efficient ESD protection circuits to sustain the required ESD level. Optimized layout rules for ESD protection in 0.13-μm silicide CMOS technology are also presented.

A novel OFDM-CPM modulation scheme and its application in WDM-PON

A novel scheme to generate, transmit, and receive an optical orthogonal frequency division multiplexing （OFDM） continuous phase modulation （CPM） signal, which is combining minimum shift keying （MSK） coding with OFDM optical modulation, for downlink application in a 4×2.5-Gb/s wavelength division multiplexing （WDM） passive optical access network, is proposed and experimentally validated. We also realize wavelength remodulation for carrying upstream on-off keying （OOK） data to reduce the cost budget at the optical network unit. The experimental results show that the power penalties for the downlink and the uplink data after transmission over 25-km SMF-28 fiber are 0.1 dB and smaller than 0.4 dB, respectively.

Impact of parasitic resistance on the ESD robustness of high-voltage devices

The impacts ofsubstrate parasitic resistance and drain ballast resistance on electrostatic discharge （ESD） robustness of LDMOS are analyzed. By increasing the two parasitic resistances, the ESD robustness of LDMOS are significantly improved. The proposed structures have been successfully verified in a 0.35μm BCD process without using additional process steps. Experimental results show that the second breakdown current of the optimal structure increases to 3,5 A, which is about 367% of the original device.