Effect and mechanism of on-chip electrostatic discharge protection circuit under fast rising time electromagnetic pulse

The electrostatic discharge(ESD)protection circuit widely exists in the input and output ports of CMOS digital circuits,and fast rising time electromagnetic pulse(FREMP)coupled into the device not only interacts with the CMOS circuit,but also acts on the protection circuit.This paper establishes a model of on-chip CMOS electrostatic discharge protection circuit and selects square pulse as the FREMP signals.Based on multiple physical parameter models,it depicts the distribution of the lattice temperature,current density,and electric field intensity inside the device.At the same time,this paper explores the changes of the internal devices in the circuit under the injection of fast rising time electromagnetic pulse and describes the relationship between the damage amplitude threshold and the pulse width.The results show that the ESD protection circuit has potential damage risk,and the injection of FREMP leads to irreversible heat loss inside the circuit.In addition,pulse signals with different attributes will change the damage threshold of the circuit.These results provide an important reference for further evaluation of the influence of electromagnetic environment on the chip,which is helpful to carry out the reliability enhancement research of ESD protection circuit.

Assessment of electrostatic discharge sensitivity of nitrogen-rich heterocyclic energetic compounds and their salts as high energy-density dangerous compounds:A study of structural variables

Nitrogen-rich heterocyclic energetic compounds(NRHECs)and their salts have witnessed widespread synthesis in recent years.The substantial energy-density content within these compounds can lead to potentially dangerous explosive reactions when subjected to external stimuli such as electrical discharge.Therefore,developing a reliable model for predicting their electrostatic discharge sensitivity(ESD)becomes imperative.This study proposes a novel and straightforward model based on the presence of specific groups(-NH_(2) or-NH-,-N=N^(+)-O^(-)and-NNO_(2),-ONO_(2) or-NO_(2))under certain conditions to assess the ESD of NRHECs and their salts,employing interpretable structural parameters.Utilizing a comprehensive dataset comprising 54 ESD measurements of NRHECs and their salts,divided into 49/5 training/test sets,the model achieves promising results.The Root Mean Square Error(RMSE),Mean Absolute Error(MAE),and Maximum Error for the training set are reported as 0.16 J,0.12 J,and 0.5 J,respectively.Notably,the ratios RMSE(training)/RMSE(test),MAE(training)/MAE(test),and Max Error(training)/Max Error(test)are all greater than 1.0,indicating the robust predictive capabilities of the model.The presented model demonstrates its efficacy in providing a reliable assessment of ESD for the targeted NRHECs and their salts,without the need for intricate computer codes or expert involvement.

A novel diode string triggered gated-Pi N junction device for electrostatic discharge protection in 65-nm CMOS technology

A novel diode string-triggered gated-Pi N junction device, which is fabricated in a standard 65-nm complementary metal-oxide semiconductor（CMOS） technology, is proposed in this paper. An embedded gated-Pi N junction structure is employed to reduce the diode string leakage current to 13 n A/μm in a temperature range from 25°C to 85°C. To provide the effective electrostatic discharge（ESD） protection in multi-voltage power supply, the triggering voltage of the novel device can be adjusted through redistributing parasitic resistance instead of changing the stacked diode number.

Structure-dependent behaviors of diode-triggered silicon controlled rectifier under electrostatic discharge stress

The comprehensive understanding of the structure-dependent electrostatic discharge behaviors in a conventional diode-triggered silicon controlled rectifier （DTSCR） is presented in this paper. Combined with the device simulation, a mathematical model is built to get a more in-depth insight into this phenomenon. The theoretical studies are verified by the transmission-line-pulsing （TLP） test results of the modified DTSCR structure, which is realized in a 65-nm complementary metal-oxide-semiconductor （CMOS） process. The detailed analysis of the physical mechanism is used to provide predictions as the DTSCR-based protection scheme is required. In addition, a method is also presented to achieve the tradeoff between the leakage and trigger voltage in DTSCR.

High holding voltage SCR for robust electrostatic discharge protection

A novel silicon controlled rectifier（SCR） with high holding voltage（Vh） for electrostatic discharge（ESD） protection is proposed and investigated in this paper. The proposed SCR obtains high Vhby adding a long N＋ layer（LN＋） and a long P＋ layer（LP＋）, which divide the conventional low voltage trigger silicon controlled rectifier（LVTSCR） into two SCRs（SCR1： P＋/Nwell/Pwell/N＋ and SCR2： P＋/LN＋/LP＋/N＋） with a shared emitter. Under the low ESD current（IESD）, the two SCRs are turned on at the same time to induce the first snapback with high V_h（V_（h1））. As the IESDincreases, the SCR2 will be turned off because of its low current gain. Therefore, the IESDwill flow through the longer SCR1 path, bypassing SCR2, which induces the second snapback with high V_h（V_（h2））. The anti-latch-up ability of the proposed SCR for ESD protection is proved by a dynamic TLP-like（Transmission Line Pulse-like） simulation. An optimized V_（h2） of 7.4 V with a maximum failure current（I_（t2）） of 14.7 m A/μm is obtained by the simulation.

Dynamic electrostatic-discharge path investigation relied on different impact energies in metal-oxide-semiconductor circuits

Gate-grounded n-channel metal-oxide-semiconductor(GGNMOS)devices have been widely implemented as power clamps to protect semiconductor devices from electrostatic discharge stress owing to their simple construction,easy triggering,and low power dissipation.We present a novel I-V characterization of the GGNMOS used as the power clamp in complementary metal-oxide-semiconductor circuits as a result of switching the ESD paths under different impact energies.This special effect could cause an unexpected latch-up or pre-failure phenomenon in some applications with relatively large capacitances from power supply to power ground,and thus should be urgently analyzed and resolved.Transmission-linepulse,human-body-modal,and light-emission tests were performed to explore the root cause.

Enhanced gated-diode-triggered silicon-controlled rectifier for robust electrostatic discharge (ESD) protection applications

A robust electron device called the enhanced gated-diode-triggered silicon-controlled rectifier (EGDTSCR) for electrostatic discharge (ESD) protection applications has been proposed and implemented in a 0.18-μm 5-V/24-V BCD process. The proposed EGDTSCR is constructed by adding two gated diodes into a conventional ESD device called the modified lateral silicon-controlled rectifier (MLSCR). With the shunting effect of the surface gated diode path, the proposed EGDTSCR, with a width of 50 μm, exhibits a higher failure current (i.e., 3.82 A) as well as a higher holding voltage (i.e., 10.21 V) than the MLSCR.

Study on electrostatic discharge(ESD)characteristics of ultra-thin dielectric film

Electrostatic discharge(ESD)event usually destroys the electrical properties of dielectric films,resulting in product failure.In this work,the breakdown characteristic of machine mode(MM)ESD on three different nano size films of head gimble assemble are obtained experimentally.The breakdown voltage and thickness parameters show a positive proportional relationship,but they are generally very low and have large discrete characteristics(~30%).The maximum and minimum breakdown voltages of the tested samples are 1.08 V and 0.46 V,which are far lower than the requirement of the current standard(25 V).In addition,the judgment criterion of product damage is given,and the relationship between discharge voltage polarity,initial resistance and breakdown voltage is studied.Finally,the theoretical analysis of the breakdown characteristic law has been given.

Enhancement of holding voltage by a modified low-voltage trigger silicon-controlled rectifier structure for electrostatic discharge protection

A novel structure of low-voltage trigger silicon-controlled rectifiers(LVTSCRs) with low trigger voltage and high holding voltage is proposed for electrostatic discharge(ESD) protection. The proposed ESD protection device possesses an ESD implant and a floating structure. This improvement enhances the current discharge capability of the gate-grounded NMOS and weakens the current gain of the silicon-controlled rectifier current path. According to the simulation results, the proposed device retains a low trigger voltage characteristic of LVTSCRs and simultaneously increases the holding voltage to 5.53 V, providing an effective way to meet the ESD protection requirement of the 5 V CMOS process.

Emerging Challenges in ESD Protection for RF ICs in CMOS

On-chip electrostatic discharge （ESD） protection design has become an emerging challenge for radio-frequency （RF） integrated circuits （IC） design as IC technologies migrate into the very-deep-sub-micron （VDSM） regime and RF ICs move into multi-GHz operations. The key problem originates from the complex interaction between the ESD protection circuitry and the core RF IC circuit under protection. This paper discusses the recent development in RF ESD protection research and design,outlining emerging challenges, new design methods,and novel RF ESD protection solutions.

High performance differential CMOS LNA design for low-IF GPS receiver

A 1.575 GHz CMOS （complementary metal-oxidesemiconductor transistor） low noise amplifier（LNA） suitable for a low intermediate frequency（IF） global positioning system（GPS） receiver is presented. Considering parasitic effects resulting from bond pad and input electrostatic discharge （ESD） protection diodes, the optimization of the input matching and noise performance is analyzed, and a narrowband inductor model is applied to the circuit design and optimization. Based on the Volterra series, the nonlinearity of the LNA is analyzed and an equation describing input-referred third-order intercept points （IIP3） which indicate the nonlinearity effects is derived; accordingly, the trade-off between the power consumption and linearity is made. The LNA is designed and simulated with TSMC （Taiwan Semiconductor Manufacturing Company） 0. 18 μm radio frequency （RF）technology. Simulation results show that the LNA has a noise figure of only 1.1 dB, - 8. 3 dBm IIP3 with 3 mA current consumption from a 1.8 V voltage supply, and the input impedances match well.

An improved GGNMOS triggered SCR for high holding voltage ESD protection applications

Developing an electrostatic discharge（ESD） protection device with a better latch-up immunity has been a challenging issue for the nanometer complementary metal-oxide semiconductor（CMOS） technology. In this work, an improved grounded-gate N-channel metal-oxide semiconductor（GGNMOS） transistor triggered silicon-controlled rectifier（SCR）structure, named GGSCR, is proposed for high holding voltage ESD protection applications. The GGSCR demonstrates a double snapback behavior as a result of progressive trigger-on of the GGNMOS and SCR. The double snapback makes the holding voltage increase from 3.43 V to 6.25 V as compared with the conventional low-voltage SCR. The TCAD simulations are carried out to verify the modes of operation of the device.

Novel substrate trigger SCR-LDMOS stacking structure for high-voltage ESD protection application

A novel substrate trigger semiconductor control rectifier-laterally diffused metal-oxide semiconductor （STSCR- LDMOS） stacked structure is proposed and simulated using the transimission line pulser （TLP） multiple-pulse simulation method in a 0.35μm, 60-V biploar-CMOS-DMOS （BCD） process without additional masks. On account of a very low holding voltage, it is susceptible to latch-up-like danger for the semiconductor control rectifier-laterally diffused metaloxide semiconductor （SCR-LDMOS） in high-voltage electro-static discharge （ESD） protection applications. Although the conventional stacking structure has achieved strong latch-up immunity by increasing holding voltage, excessive high trigger voltage does not meet requirements for an ESD protection device. The holding voltage of the proposed stacked structure is proportional to the stacking number, whereas the trigger voltage remains nearly the same. A high holding voltage of 30.6 V and trigger voltage of 75.4 V are achieved.

Low-parasitic ESD protection strategy for RF ICs in 0.35μm CMOS process

A systemic and comprehensive ESD-induced parasitic model is presented in this paper, which is used to analyse the parasitic influences of electrostatic discharge （ESD） protection circuits on the performance of radio frequency applications. A novel low-parasitic ESD protection structure is made in a 0.35μm 1P3M silicide CMOS process. The measured results show that this novel structure has a low parasitic capacitance about 310fF and a low leakage current about 12.2nA with a suitable ESD robustness target about 5kV human body model.

Terminal-optimized 700-V LDMOS with improved breakdown voltage and ESD robustness

A novel terminal-optimized triple RESURF LDMOS(TOTR-LDMOS) is proposed and verified in a 0.25-μm bipolarCMOS-DMOS(BCD) process. By introducing a low concentration region to the terminal region, the surface electric field of the TOTR-LDMOS decreases, helping to improve the breakdown voltage(BV) and electrostatic discharge(ESD) robustness. Both traditional LDMOS and TOTR-LDMOS are fabricated and investigated by transmission line pulse(TLP) tests,direct current(DC) tests, and TCAD simulations. The results show that comparing with the traditional LDMOS, the BV of the TOTR-LDMOS increases from 755 V to 817 V without affecting the specific on-resistance(R_(on,sp)) of 6.99Ω·mm^(2).Meanwhile, the ESD robustness of the TOTR-LDMOS increases by 147%. The TOTR-LDMOS exhibits an excellent performance among the present 700-V LDMOS devices.

Design of a novel high holding voltage LVTSCR with embedded clamping diode

In order to reduce the latch-up risk of the traditional low-voltage-triggered silicon controlled rectifier(LVTSCR), a novel LVTSCR with embedded clamping diode(DC-LVTSCR) is proposed and verified in a 0.18-μm CMOS process. By embedding a p+implant region into the drain of NMOS in the traditional LVTSCR, a reversed Zener diode is formed by the p+implant region and the n+bridge, which helps to improve the holding voltage and decrease the snapback region.The physical mechanisms of the LVTSCR and DC-LVTSCR are investigated in detail by transmission line pulse(TLP)tests and TCAD simulations. The TLP test results show that, compared with the traditional LVTSCR, the DC-LVTSCR exhibits a higher holding voltage of 6.2 V due to the embedded clamping diode. By further optimizing a key parameter of the DC-LVTSCR, the holding voltage can be effectively increased to 8.7 V. Therefore, the DC-LVTSCR is a promising ESD protection device for circuits with the operation voltage of 5.5–7 V.

The characteristics of primary and secondary arcs on a solar array in low earth orbit

In this paper, the characteristics of the primary arc and secondary arc on a solar array in low earth orbit（LEO） are investigated. The vacuum plasma environment in LEO has been used to study the primary arc and secondary arc of a high-voltage solar array. Silicon solar cells with rigid substrate specimens are used for the experiment. The series-parallel spacing of the silicon solar cells is 1 mm. The string currents of the solar cells are 0.7 A, 1.5 A and 2 A. The primary arc and secondary arc are photographed by high-speed cameras. The differences between the primary arc and secondary arc are observed. The secondary arc can be observed before the primary arc is extinguished. The primary arc is a single arc when the string current is 0.7 A. Multiple arc columns are accompanied by higher arc current. Two arc columns of the primary arc can be observed at 1.5 A string current and 2 A string current. The multiple primary arc columns are related to higher bias voltage. The threshold for sustained arcing is near 145 V/0.7 A, 105 V/1.5 A and 100 V/2 A at 1 mm string gap. Moreover, the transition time of secondary arc formation is analyzed, and found to be about 10–13 μs. The string currents, string voltages and primary arc have no effect on the transition time of the secondary arc formation.

Noise properties in breaking and loose contacts and their effect on quality degradation of digital signal

Electric contact discharge is subject closely related to digital information transmission, and integrity of digital signals for realizing high reliablility transmission. This kind of problem is a part of EMC (electromagnetic compatibility). From such a viewpoint, contact noise problems will be mentioned which disturb and degrade digital signals. The induction noise and radiation noise from discharge, electrostatic discharge (ESD), and connector related fundamental subject will be mentioned.

Novel LDNMOS embedded SCR with strong ESD robustness based on 0.5 μm 18 V CDMOS technology

A novel LDNMOS embedded silicon controlled rectifier(SCR) was proposed to enhance ESD robustness of high-voltage(HV) LDNMOS based on a 0.5 μm 18 V CDMOS process. A two-dimensional(2D) device simulation and a transmission line pulse(TLP) testing were used to analyze the working mechanism and ESD performance of the novel device. Compared with the traditional GG-LDNMOS, the secondary breakdown current(It2) of the proposed device can successfully increase from 1.146 A to 3.169 A with a total width of 50 μm, and ESD current discharge efficiency is improved from 0.459 m A/μm2 to 1.884 m A/μm2. Moreover, due to their different turn-on resistances(Ron), the device with smaller channel length(L) owns a stronger ESD robustness per unit area.

Design and investigation of novel ultra-high-voltage junction field-effect transistor embedded with NPN

Ultra-high-voltage(UHV)junction field-effect transistors(JFETs)embedded separately with the lateral NPN(JFETLNPN),and the lateral and vertical NPN(JFET-LVNPN),are demonstrated experimentally for improving the electrostatic discharge(ESD)robustness.The ESD characteristics show that both JFET-LNPN and JFET-LVNPN can pass the 5.5-k V human body model(HBM)test.The JFETs embedded with different NPNs have 3.75 times stronger in ESD robustness than the conventional JFET.The failure analysis of the devices is performed with scanning electron microscopy,and the obtained delayer images illustrate that the JFETs embedded with NPN transistors have good voltage endurance capabilities.Finally,the internal physical mechanism of the JFETs embedded with different NPNs is investigated with emission microscopy and Sentaurus simulation,and the results confirm that the JFET-LVNPN has stronger ESD robustness than the JFET-LNPN,because the vertical NPN has a better electron collecting capacity.The JFET-LVNPN is helpful in providing a strong ESD protection and functions for a power device.