This paper presents a debugging system for multi-pole array acoustic logging （MPAL） tools. The debugging system proposed in this study can debug the MPAL tool system, sub-system and local electronics. In the test eq...This paper presents a debugging system for multi-pole array acoustic logging （MPAL） tools. The debugging system proposed in this study can debug the MPAL tool system, sub-system and local electronics. In the test equipment, we have used principal and subordinate structures, and interconnected the host computer and the front-end machine via Ethernet. The front-end machine is based on the ARM7 （advanced reduced instruction set computing （RISC） machine） technique, the processor of which runs an embedded operating system, namely, uClinux OS. We have analyzed the system telecommunication, human-machine interface circuit, transmitter mandrel interface circuit, receiver mandrel interface circuit, and board-level test interface circuit. The software used in the system consists of the embedded front-computer software and the host application software. We have explained in detail the flow chart of the boot loader in the embedded front-computer software. The host application software is composed of four application subroutines, which match with the functional modules of the system hardware. A net communication program based on the server^client mode is implemented by means of socket programming and multi-thread programming. Test results indicate that the data transmission rate of the system is higher than 1 MB/s, which completely meets the current requirements of the data transmission rate between the tool system and the wireline telemetry device. Application of the debugging system, which includes multiple level test methods, shows that the proposed system can fully meet the test requirements of MPAL at various levels.展开更多
Serial RapidIO （SRIO） is an emerging high-performance interconnection technology for embedded systems. Protections for SRIO packets are provided by the cyclic redundancy check （CRC）. In this paper, an improved CRC...Serial RapidIO （SRIO） is an emerging high-performance interconnection technology for embedded systems. Protections for SRIO packets are provided by the cyclic redundancy check （CRC）. In this paper, an improved CRC receiving controller with 64-bit internal data width is proposed. Equivalent judgment logics are adopted in the aims of reducing the number of CRC generators. The resource consumption and power dissipation can be saved meanwhile the frequency requirement can still be met. By comparison to conventional structures, the proposed scheme can achieve better performances. Therefore, this improved receiving controller is considered applicable in high-performance SRIO interconnections.展开更多
基金supported by National Science Foundation of China (61102102, 11134011, 11204380 and 11374371)Major National Science and Technology Projects (2011ZX05020-002)+2 种基金PetroChina Innovation Foundation (2014D-5006-0307)Science and Technology Project of CNPC (2014A-3912 and 2011B-4001)the Foundation of China University of Petroleum (KYJJ2012-05-07)
文摘This paper presents a debugging system for multi-pole array acoustic logging （MPAL） tools. The debugging system proposed in this study can debug the MPAL tool system, sub-system and local electronics. In the test equipment, we have used principal and subordinate structures, and interconnected the host computer and the front-end machine via Ethernet. The front-end machine is based on the ARM7 （advanced reduced instruction set computing （RISC） machine） technique, the processor of which runs an embedded operating system, namely, uClinux OS. We have analyzed the system telecommunication, human-machine interface circuit, transmitter mandrel interface circuit, receiver mandrel interface circuit, and board-level test interface circuit. The software used in the system consists of the embedded front-computer software and the host application software. We have explained in detail the flow chart of the boot loader in the embedded front-computer software. The host application software is composed of four application subroutines, which match with the functional modules of the system hardware. A net communication program based on the server^client mode is implemented by means of socket programming and multi-thread programming. Test results indicate that the data transmission rate of the system is higher than 1 MB/s, which completely meets the current requirements of the data transmission rate between the tool system and the wireline telemetry device. Application of the debugging system, which includes multiple level test methods, shows that the proposed system can fully meet the test requirements of MPAL at various levels.
基金supported by the Special Funds for Major State Basic Research Projects(2010CB934200)
文摘Serial RapidIO （SRIO） is an emerging high-performance interconnection technology for embedded systems. Protections for SRIO packets are provided by the cyclic redundancy check （CRC）. In this paper, an improved CRC receiving controller with 64-bit internal data width is proposed. Equivalent judgment logics are adopted in the aims of reducing the number of CRC generators. The resource consumption and power dissipation can be saved meanwhile the frequency requirement can still be met. By comparison to conventional structures, the proposed scheme can achieve better performances. Therefore, this improved receiving controller is considered applicable in high-performance SRIO interconnections.
