Preparation and Properties of the Composite Enhancement Layer of Bearing Ring

In this paper, the NU308 bearing rings were subjected to strengthen grinding treatment (SGT) at ambient temperature. And the running reliabilities of specimens that subjected to SGT and conventional treatment (CT) were respectively investigated by testing dynamic properties including the running temperature, vibrations, and surface burning. Moreover, the residual stress, microtopography, and microstructures on the cross-section were respectively tested with residual stress analyzer and field-emission scanning electron microscopy. The results showed that the running reliabilities of the specimen after SGT had been significantly improved with the reduction of running temperature, vibration, and surface burning. Further study showed that the specimen’s surface was filled with disordered micropores after SGT compared to the regular strip texture on the CT specimen’s surface, and the maximum residual compressive stress induced by SGT was about −900 MPa. Moreover, the thickness of the residual compressive stress layer was over 180 µm, while the thickness of severe plastic deformation layer was about 50 µm.

Breakdown voltage model and structure realization of a thin silicon layer with linear variable doping on a silicon on insulator high voltage device with multiple step field plates

Based on the theoretical and experimental investigation of a thin silicon layer（TSL） with linear variable doping（LVD） and further research on the TSL LVD with a multiple step field plate（MSFP）,a breakdown voltage（BV） model is proposed and experimentally verified in this paper.With the two-dimensional Poisson equation of the silicon on insulator（SOI） device,the lateral electric field in drift region of the thin silicon layer is assumed to be constant.For the SOI device with LVD in the thin silicon layer,the dependence of the BV on impurity concentration under the drain is investigated by an enhanced dielectric layer field（ENDIF）,from which the reduced surface field（RESURF） condition is deduced.The drain in the centre of the device has a good self-isolation effect,but the problem of the high voltage interconnection（HVI） line will become serious.The two step field plates including the source field plate and gate field plate can be adopted to shield the HVI adverse effect on the device.Based on this model,the TSL LVD SOI n-channel lateral double-diffused MOSFET（nLDMOS） with MSFP is realized.The experimental breakdown voltage（BV） and specific on-resistance（R on,sp） of the TSL LVD SOI device are 694 V and 21.3 ·mm 2 with a drift region length of 60 μm,buried oxide layer of 3 μm,and silicon layer of 0.15 μm,respectively.

Plasma-Enhanced Atomic Layer Deposition of Amorphous Ga_(2)O_(3) for Solar-Blind Photodetection

Wide-bandgap gallium oxide(Ga_(2)O_(3))is one of the most promising semiconductor materials for solar-blind(200 nm to 280 nm)photodetection.In its amorphous form,amorphous gallium oxide(a-Ga_(2)O_(3))maintains its intrinsic optoelectronic properties while can be prepared at a low growth temperature,thus it is compatible with Si integrated circuits(ICs)technology.Herein,the a-Ga_(2)O_(3) film is directly deposited on pre-fabricated Au interdigital electrodes by plasma enhanced atomic layer deposition(PE-ALD)at a growth temperature of 250°C.The stoichiometric a-Ga_(2)O_(3) thin film with a low defect density is achieved owing to the mild PE-ALD condition.As a result,the fabricated Au/a-Ga_(2)O_(3)/Au photodetector shows a fast time response,high responsivity,and excellent wavelength selectivity for solar-blind photodetection.Furthermore,an ultra-thin MgO layer is deposited by PE-ALD to passivate the Au/a-Ga_(2)O_(3)/Au interface,resulting in the responsivity of 788 A/W(under 254 nm at 10 V),a 250-nm-to-400-nm rejection ratio of 9.2×10^(3),and the rise time and the decay time of 32 ms and 6 ms,respectively.These results demonstrate that the a-Ga_(2)O_(3) film grown by PE-ALD is a promising candidate for high-performance solar-blind photodetection and potentially can be integrated with Si ICs for commercial production.

Efficiency of Blue Organic Light-emitting Diodes Enhanced by Employing an Exciton Feedback Layer

We report that a novel exciton feedback effect is observed by introducing the bis（2-methyl-8-quinolinolato）（4- phenylphenolato）Muminum （BAlq） inserted between the emitting layer （EML） and the electron transporting layer in blue organic light emitting diodes. As an exciton feedback layer （EFL）, the BAlq does not act as a traditional hole blocking effect. The design of this kind of device structure can greatly reduce excitons＇ quenching due to accumulated space charge at the exciton formation interface. Meanwhile, the non-radiative energy transfer from EFL to the EML can also be utilized to enhance the excitons＇ formation, which is confirmed by the test of photolumimescent transient lifetime decay and electroluminescence enhancement of these devices. Accordingly, the optimal device presents the improved performances with the maximum current efficiency of 4.2 cd/A and the luminance of 24600cd/m2, which are about 1.45 times and 1.75 times higher than those of device A （control device） without the EFL, respectively. Simultaneously, the device shows an excellent color stability with a tiny offset of the CIE coordinates （△x = ±0.003, △y = ±0.004） and a relatively lower efficiency roll-off of 26.2% under the driving voltage varying from 3 V to 10 V.

Thermal Conductance of Cu and Carbon Nanotube Interface Enhanced by a Graphene Layer

Thermal conduetances between Cu and graphene covered carbon nanotubes （gCNTs） are calculated by molecular dynamics simulations. The results show that the thermal conductance is about ten times larger than that of Cu- CNT interface. The enhanced thermal conductance is due to the larger contact area introduced by the graphene layer and the stronger thermal transfer ability of the Cu-gCNT interface. From the linear increasing thermal conductance with the increasing total contact area, an effective contact area of such an interface can be defined.

Uniform, fast, and reliable CMOS compatible resistive switching memory

Resistive switching random access memory(RRAM) is considered as one of the potential candidates for next-generation memory. However, obtaining an RRAM device with comprehensively excellent performance, such as high retention and endurance, low variations, as well as CMOS compatibility, etc., is still an open question. In this work, we introduce an insert TaO_(x) layer into HfO_(x)-based RRAM to optimize the device performance. Attributing to robust filament formed in the TaO_(x) layer by a forming operation, the local-field and thermal enhanced effect and interface modulation has been implemented simultaneously. Consequently, the RRAM device features large windows(> 10^(3)), fast switching speed(-10 ns), steady retention(> 72h), high endurance(> 10^(8) cycles), and excellent uniformity of both cycle-to-cycle and device-to-device. These results indicate that inserting the TaO_(x) layer can significantly improve HfO_(x)-based device performance, providing a constructive approach for the practical application of RRAM.

Novel high-voltage power lateral MOSFET with adaptive buried electrodes

A new high-voltage and low-specific on-resistance （Ron,sp） adaptive buried electrode （ABE） silicon-on-insulator （SOI） power lateral MOSFET and its analytical model of the electric fields are proposed. The MOSFET features are that the electrodes are in the buried oxide （BOX） layer, the negative drain voltage Vd is divided into many partial voltages and the output to the electrodes is in the buried oxide layer and the potentials on the electrodes change linearly from the drain to the source. Because the interface silicon layer potentials are lower than the neighboring electrode potentials, the electronic potential wells are formed above the electrode regions, and the hole potential wells are formed in the spacing of two neighbouring electrode regions. The interface hole concentration is much higher than tile electron concentration through designing the buried layer electrode potentials. Based on the interface charge enhanced dielectric layer field theory, the electric field strength in the buried layer is enhanced. The vertical electric field EI and the breakdown voltage （BV） of ABE SOI are 545 V/μm and -587 V in the 50 μm long drift region and the 1 μm thick dielectric layer, and a low Ron,sp is obtained. Furthermore, the structure also alleviates the self-heating effect （SHE）. The analytical model matches the simulation results.

High performance AlGaN/GaN HEMTs with AlN/SiN_x passivation

A1GaN/GaN high electron-mobility transistors （HEMTs） with 5 nm A1N passivation by plasma en- hanced atomic layer deposition （PEALD） were fabricated, covered by 50 nm SiNx which was grown by plasma enhanced chemical vapor deposition （PECVD）. With PEALD A1N passivation, current collapse was suppressed more effectively and the devices show better subthreshold characteristics. Moreover, the insertion of A1N increased the RF transconductance, which lead to a higher cut-off frequency. Temperature dependence of DC characteristics demonstrated that the degradations of drain current and maximum transconductance at elevated temperatures for the A1N/SiNx passivated devices were much smaller compared with the devices with SiNx passivation, indicating that PEALD A1N passivation can improve the high temperature operation of the A1GaN/GaN HEMTs.