Quantitative analysis of the performance of vector tracking algorithms

Vector tracking changes the classical structure of receivers. Combining signal tracking and navigation solution,vector tracking can realize powerful processing capabilities by the fusion technique of receiving channel and feedback correction. In this paper,we try to break through the complicated details of numerical analysis,consider the overall influencing factors of the residual in observed data,and use the intrinsic link between a conventional receiver and a vector receiver. A simple method for performance analysis of the vector tracking algorithm is proposed. Kalman filter has the same steady performance with the classic digital lock loop through the analysis of the relation between gain and band width. The theoretical analysis by the least squares model shows that the reduction of range error is the basis for the superior performance realized by vector tracking. Thus,the bounds of its performance enhancement under weak signal and highly dynamic conditions can be deduced. Simulation results verify the effectiveness of the analysis presented here.

Quality analysis of crustal tilt and strain observations in China's earthquakes in 2014

This work analyzes the quality of crustal tilt and strain observations during 2014, which were acquired from 269 sets of ground tiltmeters and 212 sets of strainmeters. In terms of data quality, the water tube tiltmeters presented the highest rate of excellent quality,approximately 91%, and the pendulum tiltmeters and ground strainmeters yielded rates of81% and 78%, respectively. This means that a total of 380 sets of instruments produced high-quality observational data suitable for scientific investigations and analyses.

High performance 14-bit pipelined redundant signed digit ADC

A novel architecture of a pipelined redundant-signed-digit analog to digital converter（RSD-ADC） is presented featuring a high signal to noise ratio（SNR）, spurious free dynamic range（SFDR） and signal to noise plus distortion（SNDR） with efficient background correction logic. The proposed ADC architecture shows high accuracy with a high speed circuit and efficient utilization of the hardware. This paper demonstrates the functionality of the digital correction logic of 14-bit pipelined ADC at each 1.5 bit/stage. This prototype of ADC architecture accounts for capacitor mismatch, comparator offset and finite Op-Amp gain error in the MDAC（residue amplification circuit）stages. With the proposed architecture of ADC, SNDR obtained is 85.89 d B, SNR is 85.9 d B and SFDR obtained is 102.8 d B at the sample rate of 100 MHz. This novel architecture of digital correction logic is transparent to the overall system, which is demonstrated by using 14-bit pipelined ADC. After a latency of 14 clocks, digital output will be available at every clock pulse. To describe the circuit behavior of the ADC, VHDL and MATLAB programs are used. The proposed architecture is also capable of reducing the digital hardware. Silicon area is also the complexity of the design.