Design of Evolvable Hardware for Robotic Navigation

This paper presents an integrated on line learning system to evolve programmable logic array (PLA) controllers for navigating an autonomous robot in a two dimensional environment. The integrated on line learning system consists of two learning modules: one is the module of reinforcement learning based on temporal difference learning based on genetic algorithms, and the other is the module of evolutionary learning based on genetic algorithms. The control rules extracted from the module of reinforcement learning can be used as input to the module of evolutionary learning, and quickly implemented by the PLA through on line evolution. The on line evolution has shown promise as a method of learning systems in complex environment. The evolved PLA controllers can successfully navigate the robot to a target in the two dimensional environment while avoiding collisions with randomly positioned obstacles.

Evolvable Hardware Based Software-Hardware Co-Designing Platform ECDP

Based on the theories of EA （Evolutionary Algorithm） and EHW （Evolvable Hardware）, we devise an EHW based software-hardware co designing platform ECDP, on which we provided standards for hardware system encoding and evolving operation designing, as well as circuit emulating tools. The major features of this system are： two layer-encoding of circuit structure, off-line evolving with software cmulation and the evolving of genetic program designing. With this system, we implemented the auto designing of sonic software-hardware systems, like the random number generator.

Robot navigation system using intrinsic evolvable hardware

Recently there has been great interest in the idea that evolvable system based on the principle of artifcial intelligence can be used to continuously and autonomously adapt the behaviour of physically embedded systems such as autonomous mobile robots and intelligent home devices. Meanwhile, we have seen the introduction of evolvable hardware(EHW): new integrated electronic circuits that are able to continuously evolve to adapt the chages in the environment implemented by evolutionary algorithms such as genetic algorithm(GA) and reinforcement learning. This paper concentrates on developing a robotic navigation system whose basic behaviours are obstacle avoidance and light source navigation. The results demonstrate that the intrinsic evolvable hardware system is able to create the stable robotiiuc behaviours as required in the real world instead of the traditional hardware systems.

Fault self-repair strategy based on evolvable hardware and reparation balance technology

In the face of harsh natural environment applications such as earth-orbiting and deep space satellites, underwater sea vehicles, strong electromagnetic interference and temperature stress,the circuits faults appear easily. Circuit faults will inevitably lead to serious losses of availability or impeded mission success without self-repair over the mission duration. Traditional fault-repair methods based on redundant fault-tolerant technique are straightforward to implement, yet their area, power and weight cost can be excessive. Moreover they utilize all plug-in or component level circuits to realize redundant backup, such that their applicability is limited. Hence, a novel selfrepair technology based on evolvable hardware（EHW） and reparation balance technology（RBT） is proposed. Its cost is low, and fault self-repair of various circuits and devices can be realized through dynamic configuration. Making full use of the fault signals, correcting circuit can be found through EHW technique to realize the balance and compensation of the fault output-signals. In this paper, the self-repair model was analyzed which based on EHW and RBT technique, the specific self-repair strategy was studied, the corresponding self-repair circuit fault system was designed, and the typical faults were simulated and analyzed which combined with the actual electronic devices. Simulation results demonstrated that the proposed fault self-repair strategy was feasible. Compared to traditional techniques, fault self-repair based on EHW consumes fewer hardware resources, and the scope of fault self-repair was expanded significantly.

A Novel Self-adaptive Circuit Design Technique Based on Evolvable Hardware

Since traditional fault tolerance methods of electronic systems are based on redundant fault tolerance technique,and their structures are fixed when circuits are designed,the self-adaptive ability is limited.In order to solve these problems,a novel circuit self-adaptive design technique based on evolvable hardware(EHW)is proposed.It features robustness,self-organization and self-adaption.It can be adapted to a complex environment through dynamic configuration of the circuit.In this paper,the proposed technique simulated.The consumption of hardware resources and the number of convergence iterations researched.The effectiveness and superiority of the proposed technique are verified.The designed circuit has the ability of resistible redundant-state interference(RRSI).The proposed technique has a broad application prospect,and it has great significance.

Virtual reconfigurable architecture for evolving combinational logic circuits

A virtual reconfigurable architecture(VRA)-based evolvable hardware is proposed for automatic synthesis of combinational logic circuits at gate-level.The proposed VRA is implemented by a Celoxica RC1000 peripheral component interconnect(PCI)board with an Xilinx Virtex xcv2000E field programmable gate array(FPGA).To improve the quality of the evolved circuits,the VRA works through a two-stage evolution: finding a functional circuit and minimizing the number of logic gates used in a feasible circuit.To optimize the algorithm performance in the two-stage evolutionary process and set free the user from the time-consuming process of mutation parameter tuning,a self-adaptive mutation rate control(SAMRC)scheme is introduced.In the evolutionary process,the mutation rate control parameters are encoded as additional genes in the chromosome and also undergo evolutionary operations.The efficiency of the proposed methodology is tested with the evolutions of a 4-bit even parity function,a 2-bit multiplier,and a 3-bit multiplier.The obtained results demonstrate that our scheme improves the evolutionary design of combinational logic circuits in terms of quality of the evolved circuit as well as the computational effort,when compared to the existing evolvable hardware approaches.

Efficient Graph-based Genetic Programming Representation with Multiple Outputs

In this work, we explore and study the implication of having more than one output on a genetic programming （GP） graph-representation. This approach, called multiple interactive outputs in a single tree （MIOST）, is based on two ideas. First, we defined an approach, called interactivity within an individual （IWI）, which is based on a graph-GP representation. Second, we add to the individuals created with the IWI approach multiple outputs in their structures and as a result of this, we have MIOST. As a first step, we analyze the effects of IWI by using only mutations and analyze its implications （i.e., presence of neutrality）. Then, we continue testing the effectiveness of IWI by allowing mutations and the standard GP crossover in the evolutionary process. Finally, we tested the effectiveness of MIOST by using mutations and crossover and conducted extensive empirical results on different evolvable problems of different complexity taken from the literature. The results reported in this paper indicate that the proposed approach has a better overall performance in terms of consistency reaching feasible solutions.

Investigation of CAM-Brain by Using EQUnn Model

The model of EQUnn (equivalent neural network of the CAM-Brain model) is proposed. With the help of EQUnn model, it is proved that the CAM-Brain can solve the XOR problem.

Elimination-Evolution Self-repair Method for Bio-inspired Electronic System

The existing self-repair methods,evolvable hardware and embryonic electronics( embryonics) are analyzed. Based on the advantages and disadvantages of the existing self-repair methods,a novel self-repair method named elimination-evolution self-repair method is proposed. The system can be repaired through elimination in real time and evolved to optimize the allocation of system resources with this method. The proposed self-repair method not only ensures the speed of the system's self-repair,but also makes full use of system resources to improve the system's self-repair capacity and provides a new self-repair approach for bio-inspired electronic system. In the end,the advantages of the proposed eliminationevolution self-repair method are verified through a simulation experiment.

An Improved Evolvable Oscillator and Basis Function Set for Control of an Insect-Scale Flapping-Wing Micro Air Vehicle

This paper introduces an improved evolvable and adaptive hardware oscillator design capable of supporting adaptation intended to restore control precision in damaged or imperfectly manufactured insect-scale flapping-wing micro air vehicles. It will also present preliminary experimental results demonstrating that previously used basis function sets may have been too large and that significantly improved learning times may be achieved by judiciously culling the oscillator search space. The paper will conclude with a discussion of the application of this adaptive, evolvable oscillator to full vehicle control as well as the consideration of longer term goals and requirements.

Multi-objective evolutionary design of selective triple modular redundancy systems against SEUs

Abstract To improve the reliability of spaceborne electronic systems, a fault-tolerant strategy of selective triple modular redundancy （STMR） based on multi-objective optimization and evolvable hardware （EHW） against single-event upsets （SEUs） for circuits implemented on field pro- grammable gate arrays （FPGAs） based on static random access memory （SRAM） is presented in this paper. Various topologies of circuit with the same functionality are evolved using EHW firstly. Then the SEU-sensitive gates of each circuit are identified using signal probabilities of all the lines in it, and each circuit is hardened against SEUs by selectively applying triple modular redundancy （TMR） to these SEU-sensitive gates. Afterward, each circuit hardened has been evaluated by SEU Simulation, and the multi-objective optimization technology is introduced to optimize the area overhead and the number of functional errors of all the circuits, The proposed fault-tolerant strategy is tested on four circuits from microelectronics center of North Carolina （MCNC） benchmark suite. The experimental results show that it can generate innovative trade-off solutions to compromise between hardware resource consumption and system reliability. The maximum savings in the area overhead of the STMR circuit over the full TMR design is 58% with the same SEU immunity.

Optimal design of RTCs in digital circuit fault self-repair based on global signal optimization

Since digital circuits have been widely and thoroughly applied in various fields, electronic systems are increasingly more complicated and require greater reliability. Faults may occur in electronic systems in complicated environments. If immediate field repairs are not made on the faults, electronic systems will not run normally, and this will lead to serious losses. The traditional method for improving system reliability based on redundant fault-tolerant technique has been unable to meet the requirements. Therefore, on the basis of(evolvable hardware)-based and(reparation balance technology)-based electronic circuit fault self-repair strategy proposed in our preliminary work, the optimal design of rectification circuits(RTCs) in electronic circuit fault self-repair based on global signal optimization is deeply researched in this paper. First of all, the basic theory of RTC optimal design based on global signal optimization is proposed. Secondly, relevant considerations and suitable ranges are analyzed. Then, the basic flow of RTC optimal design is researched. Eventually, a typical circuit is selected for simulation verification, and detailed simulated analysis is made on five circumstances that occur during RTC evolution. The simulation results prove that compared with the conventional design method based RTC, the global signal optimization design method based RTC is lower in hardware cost, faster in circuit evolution, higher in convergent precision, and higher in circuit evolution success rate. Therefore, the global signal optimization based RTC optimal design method applied in the electronic circuit fault self-repair technology is proven to be feasible, effective, and advantageous.

Edge detection using resistive threshold logic networks with CMOS flash memories

Purpose–The purpose of this paper is to present a new approach to edge detection using semiconductor flash memory networks having scalable and parallel hardware architecture.Design/methodology/approach–A flash cell can store multiple states by controlling its voltage threshold.The equivalent resistance of the operation states controlled by threshold voltage of flash cell gives out different combinations of logic 0 and 1 states.The paper explores this basic feature of flash memory in designing a resistance change memory network for implementing novel edge detector hardware.This approach of detecting the edges is inspired from the spatial change detection ability of the human visual system.Findings–The proposed approach consumes less number of electronic components for its implementation,and outperforms the conventional approaches of edge detection with respect to the processing speed,scalability and ease of design.It is also demonstrated to provide edges invariant to changes in the direction of the spatial change in the images.Research limitations/implications–This research brings about a new direction in the development of edge detection,in terms of developing high-speed parallel processing edge detection and imaging circuits.Practical implications–The proposed approach reduces the implementation complexity by removing the need to have convolution operations for spatial edge filtering.Originality/value–This paper presents one of the first edge detection approaches that is purely a hardware oriented design,uses resistance of flash memory to form edge detector cells,and one that does not use computational operations such as additions or multiplications for its implementation.