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A Simulation Study for Typical Design Rule Patterns in 5 nm Logic Process with EUV Photolithographic Process 被引量:1
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作者 Yanli Li Qiang Wu Shoumian Chen 《Journal of Microelectronic Manufacturing》 2019年第4期33-39,共7页
5 nm logic technology node is believed to be the first node that will adopt Extremely Ultra-Violet(EUV)lithography on a large scale.We have done a simulation study for typical 5 nm logic design rule patterns.In a 5 nm... 5 nm logic technology node is believed to be the first node that will adopt Extremely Ultra-Violet(EUV)lithography on a large scale.We have done a simulation study for typical 5 nm logic design rule patterns.In a 5 nm logic photo process,the most appropriate layers for the EUV lithography are the cut layers,metal layers,and via layers.Generally speaking,critical structures in a lithography process are semi-dense patterns,also known as the“forbidden pitch”patterns,the array edge structures,tip-to-tip structures,tip-to-line structures(under 2D design rules),the minimum area structures,the bi-lines,tri-lines,…,etc.Compared to that from the 193 nm immersion process,the behaviors for the above structures are different.For example,in the 193 nm immersion process,the minimum area is about 2~3 times that of minimum pixel squared,while in EUV photolithographic process,the minimum achievable area is found to be significantly larger.In the simulation,we have kept aware of the stochastics impact due to drastically reduced number of photons absorbed compared to the DUV process,the criteria used for various structures of image contrast are tightened.For example,in 193 nm immersion lithography,we have usually set the minimum Exposure Latitude(EL)for the poly layer,the metal layer,and tip-to-tip pattern,respectively,at 18%,13%,and 10%.However,in EUV lithography,reasonable targets for the minima are,respectively,>18%,18%,and 13%.We have also studied the aberration and shadowing impact to the above design rule structures.We will present the results of our work and our explanations. 展开更多
关键词 5nm design rule minimum area minimum exposure latitude ABERRATION shadowing effect
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Overlay mark optimization for thick-film resist overlay metrology
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作者 朱亮 李杰 +2 位作者 周从树 顾以理 杨华岳 《Journal of Semiconductors》 EI CAS CSCD 北大核心 2009年第6期142-146,共5页
For thick resist implant layers,such as a high voltage P well and a deep N well,systematic and uncorrectable overlay residues brought about by the tapered resist profiles were found.It was found that the tapered profi... For thick resist implant layers,such as a high voltage P well and a deep N well,systematic and uncorrectable overlay residues brought about by the tapered resist profiles were found.It was found that the tapered profile is closely related to the pattern density.Potential solutions of the manufacturing problem include hardening the film solidness or balancing the exposure density.In this paper,instead of focusing on the process change methodology,we intend to solve the issue of the overlay metrology error from the perspective of the overlay mark design.Based on the comparison of the overlay performances between the proposed overlay mark and the original design,it is shown that the optimized overlay mark target achieves better performance in terms of profiles,dynamic precision,tool induced shift(TIS),and residues.Furthermore,five types of overlay marks with dummy bars are studied,and a recommendation for the overlay marks is given. 展开更多
关键词 overlay metrology error dynamic precision tool induced shift statistical process control depth of focus exposure latitude
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