A time-to-digital convener （TDC） oaseo on a reset-tree anti anti-harmonic oelay-locKeo oop （DLL） circuit for wireless positioning systems is discussed and described. The DLL that generates 32-phase clocks and a cy...A time-to-digital convener （TDC） oaseo on a reset-tree anti anti-harmonic oelay-locKeo oop （DLL） circuit for wireless positioning systems is discussed and described. The DLL that generates 32-phase clocks and a cycle period detector is employed to avoid ＂false locking＂. Driven by multiphase clocks, an encoder detects pulses and outputs the phase of the clock when the pulse arrives. The proposed TDC was implemented in SMIC 0.18μm CMOS technology, and its core area occupies 0.7 x 0.55 mm2. The reference frequency ranges from 20 to 150 MHz. An LSB resolution of 521 ps can be achieved by using a reference clock of 60 MHz and the DNL is less than 4-0.75 LSB. It dissipates 31.5 mW at 1.8 V supply voltage.展开更多
基金supported by the National Science and Technology Major Project(No.2011ZX03004-002-01)the Fundamental Research Funds for the Central Universities(No.WK2100230012)
文摘A time-to-digital convener （TDC） oaseo on a reset-tree anti anti-harmonic oelay-locKeo oop （DLL） circuit for wireless positioning systems is discussed and described. The DLL that generates 32-phase clocks and a cycle period detector is employed to avoid ＂false locking＂. Driven by multiphase clocks, an encoder detects pulses and outputs the phase of the clock when the pulse arrives. The proposed TDC was implemented in SMIC 0.18μm CMOS technology, and its core area occupies 0.7 x 0.55 mm2. The reference frequency ranges from 20 to 150 MHz. An LSB resolution of 521 ps can be achieved by using a reference clock of 60 MHz and the DNL is less than 4-0.75 LSB. It dissipates 31.5 mW at 1.8 V supply voltage.
