We present a design for an adaptive gain phase-locked loop （PLL） that features fast acquisition,low jitter,and wide tuning range. A dual-edge-triggered phase frequency detector （PFD） and a self-regulated voltage c...We present a design for an adaptive gain phase-locked loop （PLL） that features fast acquisition,low jitter,and wide tuning range. A dual-edge-triggered phase frequency detector （PFD） and a self-regulated voltage controlled oscillator （VCO） are employed in this design to realize the aforementioned properties. Measured results show that the experimental chip, implemented in a standard 0.5μm 5V CMOS logic process, has an acquisition time of about 150ns at 37% frequency variation and an output RMS jitter of 39ps at 640MHz.（dual-edge-triggered phase frequency detector）展开更多
We propose a novel hybrid phase-locked loop （PLL） architecture for overcoming the trade-off between fast locking time and low spur. To reduce the settling time and meanwhile suppress the reference spurs, we employ a...We propose a novel hybrid phase-locked loop （PLL） architecture for overcoming the trade-off between fast locking time and low spur. To reduce the settling time and meanwhile suppress the reference spurs, we employ a wide-band single-path PLL and a narrow-band dual-path PLL in a transient state and a steady state, respectively, by changing the loop bandwidth according to the gain of voltage controlled oscillator （VCO） and the resister of the loop filter. The hybrid PLL is implemented in a 0.18-μm complementary metal oxide semiconductor （CMOS） process with a total die area of 1.4×0.46 mm2. The measured results exhibit a reference spur level of lower than -73 dB with a reference frequency of 10 MHz and a settling time of 20 μs with 40 MHz frequency jump at 2 GHz. The total power consumption of the hybrid PLL is less than 27 mW with a supply voltage of 1.8 V.展开更多
基于直扩体制的时分多址(TDMA)卫星星座组网,信号帧前导段长度越短、净荷长度越长,数据传输的效率就越高。但是,直扩体制信号帧前导段长度越短意味着接收信号捕获增益就越低,捕获概率就越低。另外,前导段长度越短要求锁相环信号跟踪收...基于直扩体制的时分多址(TDMA)卫星星座组网,信号帧前导段长度越短、净荷长度越长,数据传输的效率就越高。但是,直扩体制信号帧前导段长度越短意味着接收信号捕获增益就越低,捕获概率就越低。另外,前导段长度越短要求锁相环信号跟踪收敛速度越快。星座组网整网数据传输效率受到卫星信号同步算法性能的制约。为了提高直扩信号同步算法的性能,从捕获与跟踪两个部分对同步算法进行了改进,提出了一种直扩信号快速同步改进算法。针对捕获部分,分析了前置低通滤波器带宽对扩频信号的自相关函数的影响,通过选择滤波器参数在保证相关主峰无明显恶化情况下提升1/4码片偏差相关峰能量1 d B以上。针对跟踪部分,提出了一种调整闭环控制系统的零极点分布优化锁相环时域响应的锁相环设计方法,给出了基于控制理论优化锁相环闭环系统的零极点分布的四点原则,利用该方法设计的锁相环能大大降低信号跟踪的收敛时间。仿真结果表明,所提改进算法与传统同步方法相比能有效提高信号的捕获概率,加快信号跟踪的收敛速度,明显减少信号的同步时间。展开更多
FMCW radars with high resolution necessities the generation of highly linear,low phase noise,and low spur chirp signals with large bandwidth and a short modulation period.This paper reviews recent research progress on...FMCW radars with high resolution necessities the generation of highly linear,low phase noise,and low spur chirp signals with large bandwidth and a short modulation period.This paper reviews recent research progress on silicon-based FMCW signal generators,identifies advances in architecture,fundamental design,performance analysis,and applications of the FMCW synthesizer.展开更多
This work presents the design and implementation of a 2.4 GHz low power fast-settling frequency-presetting PLL frequency synthesizer in the 0.18μm CMOS process.A low power mixed-signal LC VCO,a low power dual mode pr...This work presents the design and implementation of a 2.4 GHz low power fast-settling frequency-presetting PLL frequency synthesizer in the 0.18μm CMOS process.A low power mixed-signal LC VCO,a low power dual mode prescaler and a digital processor with non-volatile memory are developed to greatly reduce the power consumption and the setting time.The digital processor can automatically calibrate the presetting frequency and accurately preset the frequency of the VCO under process variations.The experimental results demonstrate that the power consumption of the synthesizer is about 4 mA @ 1.8 V and that the typical setting time of the synthesizer is less than 3μs.展开更多
文摘We present a design for an adaptive gain phase-locked loop （PLL） that features fast acquisition,low jitter,and wide tuning range. A dual-edge-triggered phase frequency detector （PFD） and a self-regulated voltage controlled oscillator （VCO） are employed in this design to realize the aforementioned properties. Measured results show that the experimental chip, implemented in a standard 0.5μm 5V CMOS logic process, has an acquisition time of about 150ns at 37% frequency variation and an output RMS jitter of 39ps at 640MHz.（dual-edge-triggered phase frequency detector）
基金supported by the National Natural Science Foundation of China(Grant No.61307128)the National Basic Research Program of China(GrantNo.2010CB327505)+1 种基金the Specialized Research Found for the Doctoral Program of Higher Education of China(Grant No.20131101120027)the Basic Research Foundation of Beijing Institute of Technology of China(Grant No.20120542015)
文摘We propose a novel hybrid phase-locked loop （PLL） architecture for overcoming the trade-off between fast locking time and low spur. To reduce the settling time and meanwhile suppress the reference spurs, we employ a wide-band single-path PLL and a narrow-band dual-path PLL in a transient state and a steady state, respectively, by changing the loop bandwidth according to the gain of voltage controlled oscillator （VCO） and the resister of the loop filter. The hybrid PLL is implemented in a 0.18-μm complementary metal oxide semiconductor （CMOS） process with a total die area of 1.4×0.46 mm2. The measured results exhibit a reference spur level of lower than -73 dB with a reference frequency of 10 MHz and a settling time of 20 μs with 40 MHz frequency jump at 2 GHz. The total power consumption of the hybrid PLL is less than 27 mW with a supply voltage of 1.8 V.
文摘基于直扩体制的时分多址(TDMA)卫星星座组网,信号帧前导段长度越短、净荷长度越长,数据传输的效率就越高。但是,直扩体制信号帧前导段长度越短意味着接收信号捕获增益就越低,捕获概率就越低。另外,前导段长度越短要求锁相环信号跟踪收敛速度越快。星座组网整网数据传输效率受到卫星信号同步算法性能的制约。为了提高直扩信号同步算法的性能,从捕获与跟踪两个部分对同步算法进行了改进,提出了一种直扩信号快速同步改进算法。针对捕获部分,分析了前置低通滤波器带宽对扩频信号的自相关函数的影响,通过选择滤波器参数在保证相关主峰无明显恶化情况下提升1/4码片偏差相关峰能量1 d B以上。针对跟踪部分,提出了一种调整闭环控制系统的零极点分布优化锁相环时域响应的锁相环设计方法,给出了基于控制理论优化锁相环闭环系统的零极点分布的四点原则,利用该方法设计的锁相环能大大降低信号跟踪的收敛时间。仿真结果表明,所提改进算法与传统同步方法相比能有效提高信号的捕获概率,加快信号跟踪的收敛速度,明显减少信号的同步时间。
基金supported by the National Key Research and Development Program of China(No.2019YFB2204700 and No.2020YFB1805004)the Beijing Municipal Science and Technology Project(No.Z191100007519005)+2 种基金Guangdong International Collaboration Program(No.2020A0505100013)Guangdong Basic and Applied Basic Research Foundation(No.2019A1515110431)the Beijing Innovation Center for Future Chips(ICFC),Tsinghua University.
文摘FMCW radars with high resolution necessities the generation of highly linear,low phase noise,and low spur chirp signals with large bandwidth and a short modulation period.This paper reviews recent research progress on silicon-based FMCW signal generators,identifies advances in architecture,fundamental design,performance analysis,and applications of the FMCW synthesizer.
基金Project supported by the National High-Tech Research and Development Program of China(Nos.2008AA010703,2009AA011606).
文摘This work presents the design and implementation of a 2.4 GHz low power fast-settling frequency-presetting PLL frequency synthesizer in the 0.18μm CMOS process.A low power mixed-signal LC VCO,a low power dual mode prescaler and a digital processor with non-volatile memory are developed to greatly reduce the power consumption and the setting time.The digital processor can automatically calibrate the presetting frequency and accurately preset the frequency of the VCO under process variations.The experimental results demonstrate that the power consumption of the synthesizer is about 4 mA @ 1.8 V and that the typical setting time of the synthesizer is less than 3μs.
