We propose a novel hybrid phase-locked loop （PLL） architecture for overcoming the trade-off between fast locking time and low spur. To reduce the settling time and meanwhile suppress the reference spurs, we employ a...We propose a novel hybrid phase-locked loop （PLL） architecture for overcoming the trade-off between fast locking time and low spur. To reduce the settling time and meanwhile suppress the reference spurs, we employ a wide-band single-path PLL and a narrow-band dual-path PLL in a transient state and a steady state, respectively, by changing the loop bandwidth according to the gain of voltage controlled oscillator （VCO） and the resister of the loop filter. The hybrid PLL is implemented in a 0.18-μm complementary metal oxide semiconductor （CMOS） process with a total die area of 1.4×0.46 mm2. The measured results exhibit a reference spur level of lower than -73 dB with a reference frequency of 10 MHz and a settling time of 20 μs with 40 MHz frequency jump at 2 GHz. The total power consumption of the hybrid PLL is less than 27 mW with a supply voltage of 1.8 V.展开更多
An S-band wideband chirp generator using specially designed fast lock phase lock loop（FL-PLL） was demonstrated.To realize high linearity,structure of direct digital synthesizer（DDS） plus FL-PLL was used.DDS gives ...An S-band wideband chirp generator using specially designed fast lock phase lock loop（FL-PLL） was demonstrated.To realize high linearity,structure of direct digital synthesizer（DDS） plus FL-PLL was used.DDS gives ideal linearity while FL-PLL retains the linearity and provides radio frequency.The system block diagrams were showed and the timing relationships of the components were provided.Two important considerations of the system,wideband loop and wideband voltage control oscillator（VCO）,were discussed;meanwhile,after analyzing the considerations,corresponding solutions were presented.Measurement results show that the generated 2560MHz to 2960MHz chirp reaches a high FM linearity of 0.003%.展开更多
基金supported by the National Natural Science Foundation of China(Grant No.61307128)the National Basic Research Program of China(GrantNo.2010CB327505)+1 种基金the Specialized Research Found for the Doctoral Program of Higher Education of China(Grant No.20131101120027)the Basic Research Foundation of Beijing Institute of Technology of China(Grant No.20120542015)
文摘We propose a novel hybrid phase-locked loop （PLL） architecture for overcoming the trade-off between fast locking time and low spur. To reduce the settling time and meanwhile suppress the reference spurs, we employ a wide-band single-path PLL and a narrow-band dual-path PLL in a transient state and a steady state, respectively, by changing the loop bandwidth according to the gain of voltage controlled oscillator （VCO） and the resister of the loop filter. The hybrid PLL is implemented in a 0.18-μm complementary metal oxide semiconductor （CMOS） process with a total die area of 1.4×0.46 mm2. The measured results exhibit a reference spur level of lower than -73 dB with a reference frequency of 10 MHz and a settling time of 20 μs with 40 MHz frequency jump at 2 GHz. The total power consumption of the hybrid PLL is less than 27 mW with a supply voltage of 1.8 V.
基金Supported by the Fund of National Defense Industry Innovative Team (231)
文摘An S-band wideband chirp generator using specially designed fast lock phase lock loop（FL-PLL） was demonstrated.To realize high linearity,structure of direct digital synthesizer（DDS） plus FL-PLL was used.DDS gives ideal linearity while FL-PLL retains the linearity and provides radio frequency.The system block diagrams were showed and the timing relationships of the components were provided.Two important considerations of the system,wideband loop and wideband voltage control oscillator（VCO）,were discussed;meanwhile,after analyzing the considerations,corresponding solutions were presented.Measurement results show that the generated 2560MHz to 2960MHz chirp reaches a high FM linearity of 0.003%.
