Event-triggered sampling and fault-tolerant control co-design based on fault diagnosis observer

A co-design scheme of event-triggered sampling mechanism and active fault tolerant control(FTC) is developed. Firstly,a fault diagnosis observer is designed to estimate both the fault and the state simultaneously by using the event-triggered sampled output. Some H∞constraints between the estimation errors and the event-triggered sampling mechanism are established to ensure the estimation accuracy. Then, based on the constraints and the obtained fault information, an event-triggered detector and a static fault tolerant controller are co-designed to guarantee the stability of the faulty system and to reduce the sensor communication cost.Furthermore, the problem of the event detector and dynamic FTC co-design is also investigated. Simulation results of an unstable batch reactor are finally provided to illustrate the effectiveness of the proposed method.

Design of Distributed Fault-Tolerant Industrial Network

A token-bus-based design method of the distributedfault-tolerant industrial network is presented in this pa-per.The dual-link network is of hot-redundancy.The performance of the network is also discussed.

Fault-Tolerant Design Techniques in ACMP Architecture

Single-chip multiprocessor (CMP) combined with the fault-loleranl(FT)techniques offers an ideal architecture to achieve high availability on the basis of sustaining highcomputing performance FT design of a single-chip multiprocessor is described, including thetechniques from hard-wart redundancy to software support and firmware strategy. The design aims atmasking the influences of errors and automatically correcting the system states.

Evolutionary Design of Fault-Tolerant Digital Circuit Based on Cartesian Genetic Programming

In many areas, reliability of the digital circuits has become the key factor to restrict circuit development. Fault-tolerant design is the commonly used method to improve the reliability of digital circuits. The current fault-tolerant design methods are based on triple modular redundancy( TMR) or multiple modular redundancy( MMR). These redundancy designs rely on the experience of the designers,and the designed circuits have poor adaptabilities to a complex environment. However, evolutionary design of digital circuits does not rely on prior knowledge. During the evolution, some novel and optimal circuit topologies can be found, and the evolved circuits can feature strong adaptive capacities. Based on Cartesian genetic programming( CGP), a novel method for designing fault-tolerant digital circuits by evolution is proposed,key steps of the evolution are introduced,influences of function sets on evolution are investigated,and as a preliminary result,an evolved full adder with high fault-tolerance is shown.

Fault-tolerant Strategies and Their Design Methods for Application Software

The key to software reliability is fault-tolerant design ofapplication software.New fault-tolerant strategies andtheir design methods for application software under vari-ous computer system are introduced.It has such advan-tages as simple hardware platform,independent fromapplication,stable reliability.lastly,some technicalproblems are discussed in details.

Research on robust fault-tolerant control for networked control system with packet dropout

A kind of networked control system with network-induced delay and packet dropout, modeled on asynchronous dynamical systems was tested, and the integrity design of the networked control system with sensors failures and actuators failures was analyzed using hybrid systems technique based on the robust fault-tolerant control theory. The parametric expression of controller is given based on the feasible solution of linear matrix inequality. The simulation results are provided on the basis of detailed theoretical analysis, which further demonstrate the validity of the proposed schema.

Design and Test of Multibus Adapter System on a Chip for Fault Tolerant Computer Systems

In order to improve the system reliability and performance and to reduce the system cost, volume and weight, we have designed, fabricated and tested the multibus adapter system of a trimodular redundant fault tolerant computer system on a single chip of 5000 gate CMOS gate array. The design, fabrication and test of this single chip system will be discussed..

Energy-aware Load-balaning Fault-tolerant Routing Scheme for Ad hoc Sensor Networks

Most routing protocols for sensor networks try to extend network lifetime by minimizing the energy consumption, but have not taken the network reliability into account. An energy-aware, load-balancing and fault-tolerant routing scheme, termed as ELFR was propsed to adapt to the harsh environment. First a network robustness model was presented. Based on this model, the route discovery phase was designed to make the sensors to construct into a hop-leveled network which is mesh structure. A cross-layer design was adopted to measure the transmission delay so as to detect the failed nodes. The routing scheme works with acknowledge (ACK) feedback mechanism to transfer control messages to avoid producing extra control overhead messages. When nodes fail, the new healthy paths will be selected locally without rerouting. Simulation results show that our scheme is much robust, and it achieves better energy efficiency, load balancing and maintains good end-to-end delay.

Toward a Multi-Hop, Multi-Path Fault-Tolerant and Load Balancing Hierarchical Routing Protocol for Wireless Sensor Network

This paper describes a novel energy-aware multi-hop cluster-based fault-tolerant load balancing hierarchical routing protocol for a self-organizing wireless sensor network (WSN), which takes into account the broadcast nature of radio. The main idea is using hierarchical fuzzy soft clusters enabling non-exclusive overlapping clusters, thus allowing partial multiple membership of a node to more than one cluster, whereby for each cluster the clusterhead (CH) takes in charge intra-cluster issues of aggregating the information from nodes members, and then collaborate and coordinate with its related overlapping area heads (OAHs), which are elected heuristically to ensure inter-clusters communication. This communication is implemented using an extended version of time-division multiple access (TDMA) allowing the allocation of several slots for a given node, and alternating the role of the clusterhead and its associated overlapping area heads. Each cluster head relays information to overlapping area heads which in turn each relays it to other associated cluster heads in related clusters, thus the information propagates gradually until it reaches the sink in a multi-hop fashion.

A New Approach to Robust and Fault Tolerant Control

In this paper, we shall summarize a new approach to robust and fault tolerant control proposed recently by the author. This approach is based on a variation of all controller parametrization. This robust and fault-tolerant control design consists of two parts: a nominal performance controller and a robustness controller, and works in such a way that when a component (sensor,actuator, etc.) failure is detected, the controller structure is reconfigured by adding a robustness loop to compensate the fault. We shall illustrate how this strategy works under various situations.

Separation of Fault Tolerance and Non-Functional Concerns: Aspect Oriented Patterns and Evaluation

Dependable computer based systems employing fault tolerance and robust software development techniques demand additional error detection and recovery related tasks. This results in tangling of core functionality with these cross cutting non-functional concerns. In this regard current work identifies these dependability related non-functional and cross-cutting concerns and proposes design and implementation solutions in an aspect oriented framework that modularizes and separates them from core functionality. The degree of separation has been quantified using software metrics. A Lego NXT Robot based case study has been completed to evaluate the proposed design framework.

基于相关性分离的逻辑电路敏感门定位算法

随着CMOS器件特征尺寸进入纳米量级,因高能粒子辐射等造成的电路失效问题日益严重,给电路可靠性带来严峻挑战。现阶段,准确评估集成电路可靠性,并以此为依据对电路进行容错加固,以提高电路系统可靠性变得刻不容缓。然而,由于逻辑电路中存在大量扇出重汇聚结构,由此引发的信号相关性导致可靠性评估与敏感单元定位面临困难。该文提出一种基于相关性分离的逻辑电路敏感门定位算法。先将电路划分为多个独立电路结构(ICS);以ICS为基本单元分析故障传播及信号相关性影响;再利用相关性分离后的电路模块和反向搜索算法精准定位逻辑电路敏感门单元;最后综合考虑面向输入向量空间的敏感门定位及针对性容错加固。实验结果表明,所提算法能准确、高效地定位逻辑电路敏感单元,适用于大规模及超大规模电路的可靠性评估与高效容错设计。

老龄化背景下的体感交互容错设计路径研究

本研究基于老年人体感交互过程中的行为差错与老年体感交互设计案例,探讨老年人体感交互容错设计的可行路径。通过对老年人的体感交互的现状与老年人的行为差错分析,回顾了大量的老年人容错设计应用性研究,结合案例分析梳理了文献考证、图像分析等研究方法。总结、提取了老年人体感交互容错设计路径,有助于体感交互在结构框架层、交互层、设计层等方面进行适老化容错设计,为老年人体感交互以及其他交互领域提供容错思路,从而设计出满足老年用户需求的交互动作、手势、界面等。

基于BU-61580总线控制器的接口及容错设计

针对RS-422接口与1553B总线接口无法直接进行高可靠性数据通信,提出了一种基于BU-61580总线控制器的接口及容错设计;设计采用1553B接口芯片BU-61580,通过FPGA控制完成了RS-422与1553B的接口控制及二者之间的数据处理;在硬件接口设计的基础上,设计IP-CORE完成BU-61580的芯片配置,并通过增加容错设计提高了总线控制器数据通信的可靠性;经测试结果显示,计算机通过总线控制器与RT终端通信稳定、可靠,并应用于某测试系统中。

基于二阶边缘检测算法的随机架构设计

数字图像边缘是具有明显亮度变化的像素集合,边缘检测是识别图像边缘的最佳方法。其中,二阶边缘检测算法具有很强的边缘定位能力,但在硬件实现上需要消耗大量资源,且易受到电路的内部噪声影响。文章提出拉普拉斯(Laplace)和高斯拉普拉斯(Laplacian of Gaussian,LoG)2种常见二阶边缘检测算法的随机电路结构,并控制输入比特流的相关性来优化电路,进一步提高运行效率。实验结果表明,相比于传统的加权二进制实现,该电路消耗更少的功耗和电路面积,同时拥有更高的容错性。

基于SCADA数据协同的风力机故障检测与控制

为了在不停机的前提下,安全可靠地对齿轮箱进行故障检测,并实现风力发电机在齿轮箱故障工况下的容错控制运行,提出一种基于标准数据采集与监视控制(SCADA)数据协同的风力机故障检测与控制方案。介绍了风力发电机的系统模型与SCADA解决方案框架,通过回归建模、异常分析和集成学习对风力发电机系统进行故障检测并获得健康指标;借助模糊逻辑控制对风力发电机的输出功率进行降额控制,从而实现风力发电机在齿轮箱故障工况下的容错控制运行,最后进行仿真实验,并将仿真结果与一个实际运行的2 MW风力发电机系统进行对比。实验结果表明:该故障检测与容错控制方案可以有效地对齿轮箱进行故障检测,并在存在故障时适当对风力发电机的输出功率进行降额控制,从而降低叶片和塔架承受的应力,并有效降低了齿轮箱轴承和润滑油的温度。

3D-IC中基于时分复用的TSV蜂窝容错设计

三维芯片(3D-IC)通过硅通孔(TSV)技术来实现电路的垂直互连,延续了摩尔定律,但在制造、绑定等过程中,TSV容易引入各类缺陷。添加冗余TSV是解决该问题的有效方法之一,但TSV面积开销大、制造成本高。提出一种基于时分复用(TDMA)的TSV蜂窝结构容错设计方案,它基于时间对信号TSV进行复用。实验结果表明,与一维链式TDMA结构相比,蜂窝TDMA结构提高了30%的故障覆盖率,并且故障覆盖率随着蜂窝阵列的扩展持续提升。在64TSV阵列中,与一维TDMA结构相比,蜂窝拓扑结构的面积开销降低了10.4%。

Self-healing and SDN:bridging the gap

Achieving high programmability has become an essential aim of network research due to the ever-increasing internet traffic.Software-Defined Network(SDN)is an emerging architecture aimed to address this need.However,maintaining accurate knowledge of the network after a failure is one of the largest challenges in the SDN.Motivated by this reality,this paper focuses on the use of self-healing properties to boost the SDN robustness.This approach,unlike traditional schemes,is not based on proactively configuring multiple(and memory-intensive)backup paths in each switch or performing a reactive and time-consuming routing computation at the controller level.Instead,the control paths are quickly recovered by local switch actions and subsequently optimized by global controller knowledge.Obtained results show that the proposed approach recovers the control topology effectively in terms of time and message load over a wide range of generated networks.Consequently,scalability issues of traditional fault recovery strategies are avoided.

一种星载在轨神经网络的容错设计方法

为了满足高可靠星载在轨实时舰船目标检测的应用需求,该文针对基于神经网络的合成孔径雷达(SAR)舰船检测提出了一种容错加固设计方法。该方法以轻量级网络MobilenetV2为检测模型框架,对模型在现场可编程逻辑阵列(FPGA)的加速处理进行实现,基于空间单粒子翻转(SEU)对网络的错误模型进行分析,将并行化加速设计思想与高可靠三模冗余(TMR)思想进行融合,优化设计了基于动态重配置的部分三模容错架构。该容错架构通过多个粗粒度计算单元进行多图像同时处理,多单元表决进行单粒子翻转自检与恢复,经实际图像回放测试,FPGA实现的帧率能有效满足在轨实时处理需求。通过模拟单粒子翻转进行容错性能测试,相对原型网络该容错设计方法在资源消耗仅增加不到20%的情况下,抗单粒子翻转检测精度提升了8%以上,相较传统容错设计方式更适合星载在轨应用。

基于系统韧性理论的城市轨道交通信号系统设计

“故障-持续运行”是对城市轨道交通信号系统的最高要求,也是基于运营高度对系统安全的理解。在自动化系统不断扩展其功能边界的趋势下,人员介入不再被认为是安全可靠的手段,系统本身应能处理更多的异常。分析了与系统可靠性相关的容错、安全完整性和韧性的概念;将系统韧性理论引入城市轨道交通信号系统设计,采用系统能力损失对系统韧性进行量化计算;建立了韧性系统设计模型,并将该模型应用于智能调度系统设计,使用韧性度量来作为最优化控制目标。仿真验证证明了系统韧性理论和方法在城市轨道交通信号系统设计中的有效性。