The paper presents structure-oriented Register Transfer Level (RTL) test generation algorithm, which hierarchically tests large-scale circuits. It generates tests for low-level circuit with gate-level test generation ...The paper presents structure-oriented Register Transfer Level (RTL) test generation algorithm, which hierarchically tests large-scale circuits. It generates tests for low-level circuit with gate-level test generation technology, and generates tests for high-level circuit with combining module test sets. It also presents a new fault-simulation algorithm at RT level circuit to adapt test generation hierarchically.展开更多
基金supported by National Natural Science Foundation of China under the grant No.69733010,69973016
文摘The paper presents structure-oriented Register Transfer Level (RTL) test generation algorithm, which hierarchically tests large-scale circuits. It generates tests for low-level circuit with gate-level test generation technology, and generates tests for high-level circuit with combining module test sets. It also presents a new fault-simulation algorithm at RT level circuit to adapt test generation hierarchically.
