A newΣΔmodulator architecture for thermal vacuum sensor ASICs is proposed.The micro-hotplate thermal vacuum sensor fabricated by surface-micrornachining technology can detect the gas pressure from 1 to 10;Pa. The am...A newΣΔmodulator architecture for thermal vacuum sensor ASICs is proposed.The micro-hotplate thermal vacuum sensor fabricated by surface-micrornachining technology can detect the gas pressure from 1 to 10;Pa. The amplified differential output voltage signal of the sensor feeds to theΣΔmodulator to be converted into digital domain.The presentedΣΔmodulator makes use of a feed-forward path to suppress the harmonic distortions and attain high linearity.Compared with other feed-forward architectures presented before,the circuit complexity,chip area and power dissipation of the proposed architecture are significantly decreased.The correlated double sampling technique is introduced in the 1st integrator to reduce the flicker noise.The measurement results demonstrate that the modulator achieves an SNDR of 79.7 dB and a DR of 80 dB over a bandwidth of 7.8 kHz at a sampling rate of 4 MHz.The circuit has been fabricated in a 0.5μm 2P3M standard CMOS technology.It occupies an area of 5 mm;and dissipates 9 mW from a single 3 V power supply.The performance of the modulator meets the requirements of the considered application.展开更多
基金Project supported by the National Natural Science Foundation of China(No.90607003).
文摘A newΣΔmodulator architecture for thermal vacuum sensor ASICs is proposed.The micro-hotplate thermal vacuum sensor fabricated by surface-micrornachining technology can detect the gas pressure from 1 to 10;Pa. The amplified differential output voltage signal of the sensor feeds to theΣΔmodulator to be converted into digital domain.The presentedΣΔmodulator makes use of a feed-forward path to suppress the harmonic distortions and attain high linearity.Compared with other feed-forward architectures presented before,the circuit complexity,chip area and power dissipation of the proposed architecture are significantly decreased.The correlated double sampling technique is introduced in the 1st integrator to reduce the flicker noise.The measurement results demonstrate that the modulator achieves an SNDR of 79.7 dB and a DR of 80 dB over a bandwidth of 7.8 kHz at a sampling rate of 4 MHz.The circuit has been fabricated in a 0.5μm 2P3M standard CMOS technology.It occupies an area of 5 mm;and dissipates 9 mW from a single 3 V power supply.The performance of the modulator meets the requirements of the considered application.
