Improvement of switching characteristics by substrate bias in AlGaN/AlN/GaN heterostructure field effect transistors

A simple and effective approach to improve the switching characteristics of AlGaN/AlN/GaN heterostructure field effect transistors （HFETs） by applying a voltage bias on the substrate is presented. With the increase of the substrate bias, the OFF-state drain current is much reduced and the ON-state current keeps constant. Both the ON/OFF current ratio and the subthreshold swing are demonstrated to be greatly improved. With the thinned substrate, the improvement of the switching characteristics with the substrate bias is found to be even greater. The above improvements of the switching characteristics are attributed to the interaction between the substrate bias induced electrical field and the bulk traps in the GaN buffer layer, which reduces the conductivity of the GaN buffer layer.

SiC MOSFET开关瞬态解析建模综述

在评估和优化半导体器件开关瞬态特性领域,解析模型因具有简单、直观、应用便捷等优点得到广泛研究。相较同等功率等级的硅基功率器件,碳化硅(silicon carbide,SiC)金属氧化物半导体场效应晶体管(metal-oxide-semiconductor field effect transistor,MOSFET)可以应用于更高开关速度,其开关瞬态特性更为复杂,开关瞬态解析建模也更加困难。该文总结现有的针对SiC MOSFET与二极管换流对的开关瞬态解析建模方法,在建模过程中依次引入各种简化假设,按照简化程度由低到高的顺序,梳理解析建模的逐步简化过程。通过对比,评估各模型的优缺点以及适用场合,对其中准确性、实用性都较强的分段线性模型进行详细介绍;之后,对开关瞬态建模中关键参数的建模方法进行总结与评价;最后,指出现有SiC MOSFET开关瞬态解析模型中存在的问题,并对其未来发展给出建议。

Progress of power field effect transistor based on ultra-wide bandgap Ga_2O_3 semiconductor material

As a promising ultra-wide bandgap semiconductor, gallium oxide(Ga_2O_3) has attracted increasing attention in recent years. The high theoretical breakdown electrical field(8 MV/cm), ultra-wide bandgap(～ 4.8 eV) and large Baliga's figure of merit(BFOM) of Ga_2O_3 make it a potential candidate material for next generation high-power electronics, including diode and field effect transistor(FET). In this paper, we introduce the basic physical properties of Ga_2O_3 single crystal, and review the recent research process of Ga_2O_3 based field effect transistors. Furthermore, various structures of FETs have been summarized and compared, and the potential of Ga_2O_3 is preliminary revealed. Finally, the prospect of the Ga_2O_3 based FET for power electronics application is analyzed.

Review of gallium oxide based field-effect transistors and Schottky barrier diodes

Gallium oxide(Ga_2O_3), a typical ultra wide bandgap semiconductor, with a bandgap of ~4.9 e V, critical breakdown field of 8 MV/cm, and Baliga's figure of merit of 3444, is promising to be used in high-power and high-voltage devices.Recently, a keen interest in employing Ga_2O_3 in power devices has been aroused. Many researches have verified that Ga_2O_3 is an ideal candidate for fabricating power devices. In this review, we summarized the recent progress of field-effect transistors(FETs) and Schottky barrier diodes(SBDs) based on Ga_2O_3, which may provide a guideline for Ga_2O_3 to be preferably used in power devices fabrication.

Low working loss Si/4H-SiC heterojunction MOSFET with analysis of the gate-controlled tunneling effect

A silicon (Si)/silicon carbide (4H-SiC) heterojunction double-trench metal-oxide-semiconductor field effect transistor (MOSFET) (HDT-MOS) with the gate-controlled tunneling effect is proposed for the first time based on simulations. In this structure, the channel regions are made of Si to take advantage of its high channel mobility and carrier density. The voltage-withstanding region is made of 4H-SiC so that HDT-MOS has a high breakdown voltage (BV) similar to pure 4H-SiC double-trench MOSFETs (DT-MOSs). The gate-controlled tunneling effect indicates that the gate voltage (V_(G)) has a remarkable influence on the tunneling current of the heterojunction. The accumulation layer formed with positive VG can reduce the width of the Si/SiC heterointerface barrier, similar to the heavily doped region in an Ohmic contact. This narrower barrier is easier for electrons to tunnel through, resulting in a lower heterointerface resistance. Thus, with similar BV (approximately 1770 V), the specific on-state resistance (R_(ON-SP)) of HDT-MOS is reduced by 0.77 mΩ·cm^(2) compared with that of DT-MOS. The gate-to-drain charge (Q_(GD)) and switching loss of HDT-MOS are 52.14% and 22.59% lower than those of DT-MOS, respectively, due to the lower gate platform voltage (V_(GP)) and the corresponding smaller variation (ΔV_(GP)). The figure of merit (Q_(GD)×R_(ON-SP)) of HDT-MOS decreases by 61.25%. Moreover, the heterointerface charges can reduce RON-SP of HDT-MOS due to trap-assisted tunneling while the heterointerface traps show the opposite effect. Therefore, the HDT-MOS structure can significantly reduce the working loss of SiC MOSFET, leading to a lower temperature rise when the devices are applied in the system.

Electrically Tunable Energy Bandgap in Dual-Gated Ultra-Thin Black Phosphorus Field Effect Transistors

The energy bandgap is an intrinsic character of semiconductors, which largely determines their properties. The ability to continuously and reversibly tune the bandgap of a single device during real time operation is of great importance not only to device physics but also to technological applications. Here we demonstrate a widely tunable bandgap of few-layer black phosphorus （BP） by the application of vertical electric field in dual-gated BP field-effect transistors. A total bandgap reduction of 124 meV is observed when the electrical displacement field is increased from 0.10 V/nm to 0.83 V/nm. Our results suggest appealing potential for few-layer BP as a tunable bandgap material in infrared optoelectronies, thermoelectric power generation and thermal imaging.

The study on mechanism and model of negative bias temperature instability degradation in P-channel metal-oxide-semiconductor field-effect transistors

Negative Bias Temperature Instability （NBTI） has become one of the most serious reliability problems of metaloxide-semiconductor field-effect transistors （MOSFETs）. The degradation mechanism and model of NBTI are studied in this paper. From the experimental results, the exponential value 0.25-0.5 which represents the relation of NBTI degradation and stress time is obtained. Based on the experimental results and existing model, the reaction-diffusion model with H^＋ related species generated is deduced, and the exponent 0.5 is obtained. The results suggest that there should be H^＋ generated in the NBTI degradation. With the real time method, the degradation with an exponent 0.5 appears clearly in drain current shift during the first seconds of stress and then verifies that H^＋ generated during NBTI stress.

Determining the influence of ferroelectric polarization on electrical characteristics in organic ferroelectric field-effect transistors

Organic ferroelectric field-effect transistors （OFeFETs） are regarded as a promising technology for low-cost flexible memories. However, the electrical instability is still a critical obstacle, which limits the commercialization process. Based on already established models for polarization in ferroelectrics and charge transport in OFeFETs, simulation work is performed to determine the influence of polarization fatigue and ferroelectric switching transient on electrical characteristics in OFeFETs. The polarization fatigue results in the decrease of the on-state drain current and the memory window width and thus degrades the memory performance. The output measurements during the ferroelectric switching process show a hysteresis due to the instable polarization. In the on/off measurements, a large writing/erasing pulse frequency weakens the polarization modulation and thus results in a small separation between on- and off-state drain currents. According to the electrical properties of the ferroelectric layer, suggestions are given to obtain optimal electrical characterization for OFeFETs.

用于SiC MOSFET开关电压测量的非接触式电场耦合电压传感器

准确测量碳化硅(silicon carbide,SiC)金属–氧化物半导体场效应晶体管(metal-oxide-semiconductor field-effect transistor,MOSFET)开关电压是评估SiC MOSFET开关特性、计算开关损耗、优化变换器设计的关键。随着SiC MOSFET开关速度、耐压及功率密度的提升,开关电压测量难的问题逐渐凸显,因此对电压传感器的带宽、耐压和侵入性提出了新的要求。该文以SiC MOSFET的开关电压为研究对象,根据目前开关电压的测量需求,提出一种利用电场耦合原理测量开关电压的非接触式电压传感器,并设计混合积分电路对传感器输出信号进行电压重构。在此基础上,通过仿真和计算着重分析电场耦合电压传感器的结构和电路参数的设计依据。传感器带宽范围为5Hz~260MHz,量程为-1000~+1000V,输入电容约为0.73pF,最后利用双脉冲测试,将其与商用示波器探头的测量结果进行对比,验证电场耦合电压传感器的准确性。

负载大小对SiC MOSFET开关速度的影响

现有研究多关注驱动电阻、驱动电压、寄生参数等对碳化硅(SiC)金属氧化物半导体场效应晶体管(MOSFET)开关特性的影响,鲜有文献研究负载大小的影响。针对负载大小影响SiC MOSFET开关速度这一现象,建立开关过程模型,结合其转移特性分析此现象产生的原因,仿真和理论分析表明,SiC MOSFET的开通速度随负载增大而降低,关断速度随负载增大而增加。使用SiC功率模块进行双脉冲测试,结果验证了理论分析的正确性。

Comparative Performance Evaluation of Large FPGAs with CNFET-and CMOS-based Switches in Nanoscale

Routing resources are the major bottlenecks in improving the performance and power consumption of the current FPGAs. Recently reported researches have shown that carbon nanotube field effect transistors(CNFETs) have considerable potentials for improving the delay and power consumption of the modern FPGAs. In this paper, hybrid CNFET-CMOS architecture is presented for FPGAs and then this architecture is evaluated to be used in modern FPGAs. In addition, we have designed and parameterized the CNFET-based FPGA switches and calibrated them for being utilized in FPGAs at 45 nm, 22 nm and 16 nm technology nodes.Simulation results show that the CNFET-based FPGA switches improve the current FPGAs in terms of performance, power consumption and immunity to process and temperature variations. Simulation results and analyses also demonstrate that the performance of the FPGAs is improved about 30%, on average and the average and leakage power consumptions are reduced more than 6% and 98% respectively when the CNFET switches are used instead of MOSFET FPGA switches. Moreover, this technique leads to more than 20.31%smaller area. It is worth mentioning that the advantages of CNFET-based FPGAs are more considerable when the size of FPGAs grows and also when the technology node becomes smaller.

基于FET生物传感器的病原微生物检测系统设计

设计了一种基于场效应管(FET)生物传感器的检测系统。以STM32F103微处理器集成了自动进样、温度控制、光调制、数据采集与放大等模块;同时完成了基于C++软件环境的数据处理与分析人机交互界面的设计。通过对整个系统性能测试实验分析,结果表明:该系统检测灵敏度高,响应速度快,性能稳定可靠,抗干扰性强,操作简单、便携,能够较好地满足现场快速检测病原微生物的需求。

不同温度下JLNT-FET和IMNT-FET的模拟/射频特性

无结纳米管场效应晶体管(JLNT-FET)和反转模式纳米管场效应晶体管(IMNT-FET)因具有较好的驱动能力和对短沟道效应(SCE)卓越的抑制能力被广泛研究。基于Sentaurus TCAD数值模拟,分析了环境温度对JLNT-FET和IMNT-FET的模拟/射频(RF)特性的影响,对比研究了JLNT-FET和IMNT-FET由于掺杂浓度和传导方式不同导致的性能差异。结果表明,随着温度升高,载流子声子散射加剧,器件的寄生电容增加,导致器件的模拟/RF性能下降。体传导的JLNT-FET受到声子散射影响较小,所以其漏源电流受温度影响比表面传导的IMNT-FET小。另外,JLNT-FET的载流子迁移率受沟道重掺杂影响,导致其驱动能力和模拟/RF性能都比IMNT-FET差。研究结果对进一步优化这两类器件及其在电路中的应用具有一定的参考意义。

碳化硅MOSFET并联技术研究

碳化硅功率器件具有更高的开关频率和耐压特性,为了提高碳化硅功率驱动的过流能力,同时降低引线电感,设计一个由4个碳化硅金属氧化物半导体场效应晶体管(Metal-Oxide-Semiconductor Field-Effect Transistor,MOSFET)并联的驱动模块。详细介绍了栅驱动器原理、印制电路板(Printed Circuit Board,PCB)布局以及静态和动态均流性能波形,通过分析验证了电阻等器件参数的差异对均流的影响。

基于MOSFET的固体调制器研究

固体调制器能产生短脉冲、快上升沿、快下降沿、大电流,并能工作在兆赫兹频率下,因此是脉冲功率技术的一个重要发展方向。介绍了由功率金属氧化物半导体场效应晶体管(MOSFET)器件组成的固体调制器的基本工作原理。采用单片机和CPLD作为硬件核心设计了脉冲信号发生器,作为固体调制器的触发信号源。通过对驱动电路的仿真,确定了由集成驱动芯片组成的驱动电路的主要参数;设计了6个MOSFET并联的开关模块。实验表明,其具有良好的静态、动态均流效果。最终设计的调制器由3个开关模块叠加而成,在800V充电电压下,可以得到最短脉宽为33.8ns,前沿为13.9ns,幅度为2.20kV的脉冲。在多脉冲情况下,脉冲的一致性良好。

功率MOSFET反向特性的分析模拟

本文对功率MOSFET的反向特性进行了模拟，着重分析了N沟功率MOSFET体内集成二极管的独特的作用，并对P沟器件在特性模拟时由于PSPICE模型参数的限制而表现出来的误差进行了分析，提出了改善措施，并得到了与实际相符合的结论．

过渡金属二硫族化合物在FET中的应用研究进展

过渡金属二硫族化合物(Transition-metal dichalcogenides,TMDs)作为一组二维材料具有丰富的物理特性,近几年因其半导特性在半导体器件上具有重要的应用前景而引其了学界的普遍关注。总结了TMDs材料的制备方法及其在场效应管(FET)上的应用研究进展,并对存在的问题以及潜在的研究方向做了展望。

GaAs开关FET功率特性的研究

在GaAs单片微波集成电路(MMIC)设计中,开关场效应晶体管(FET)是研制开关、数控衰减器、数控移相器等电路的基础。基于0.15μm栅长GaAs开关FET,研究了GaAs开关FET在低频下的功率压缩特性。通过对开关FET的小信号等效电路和大信号模型的分析,发现频率下降会降低开关FET的栅压,从而降低开关FET低频下的功率容量。通过增加栅极电阻来提高栅极电压,进而增加开关FET功率容量。最后通过实际的开关电路验证了增大栅极电阻可有效提高开关电路的功率容量,对今后的开关类器件设计工作起到一定的指导意义。

高效率GaAs/InGaAsHFET功率放大器

研制成 Ga As/ In Ga As异质结功率 FET(HFET) ,该器件是在常规的高 -低 -高分布 Ga As MESFET的基础上 ,在有源层的尾部引入 i-In Ga As层。采用 HFET研制的两级 C波功率放大器 ,在 5 .0～ 5 .5 GHz带内 ,当Vds=5 .5 V时 ,输出功率大于 3 2 .3 1 d Bm(0 .1 77W/ mm ) ,功率增益大于 1 9.3 d B,功率附加效率 (PAE)大于3 8.7% ,PAE最大达到 49.4% ,该放大器在 Vds=9.0 V时 ,输出功率大于 3 6.65 d Bm(0 .48W/ mm) ,功率增益大于 2 1 .6d B,PAE典型值 3 5 %

基于各向异性导电膜的射频SP8T开关无损测试

为了解决射频器件无损测试的难点,基于各向异性导电膜Z轴(ACF-Z)连接结构,设计并实现了射频器件无损测试技术。针对表面贴装式GaAs金属半导体场效应晶体管(MESFET)单刀八掷(SP8T)开关,该测试技术使用ACF-Z轴连接结构实现器件与测试板的无损连接,通过矢量网络分析仪对GaAs MESFET SP8T开关性能进行测试,最多可同时测试SP8T开关的8个通道。测试结果显示,1~8 GHz内,器件的插入损耗为-15~-35 dB,回波损耗为-15~-35 dB,测试过程中未对器件造成损伤。