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一款基于新型Field Programmable Gate Array芯片的投影仪梯形校正系统研究与实现 被引量:5
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作者 曹凤莲 沈庆宏 +1 位作者 盛任农 高敦堂 《南京大学学报(自然科学版)》 CAS CSCD 北大核心 2006年第4期362-367,共6页
投影设备配备的梯形校正普遍存在校正范围小,画面的一些线条和字符边缘会出现毛刺和不平滑现象,矫正效果不理想.如果采用通用的图像处理芯片和复杂的算法,可以解决上述问题,但又会导致成本急剧上升.为了解决上述矛盾,提出一种基于FPGA(F... 投影设备配备的梯形校正普遍存在校正范围小,画面的一些线条和字符边缘会出现毛刺和不平滑现象,矫正效果不理想.如果采用通用的图像处理芯片和复杂的算法,可以解决上述问题,但又会导致成本急剧上升.为了解决上述矛盾,提出一种基于FPGA(Field Programmable Gate Array)芯片的新型梯形校正实现方案,解决了校正范围与锯齿失真的矛盾问题,并为进一步成为芯片级产品铺平了道路.图像处理采用kaiser窗函数和sinc函数相结合的方法进行插值,这样的滤波器改善了旁瓣抑制,具有较好的通带性能.介绍了梯形失真的产生和校正原理,提出了利用FPGA芯片XC3S400作为核心图像处理单元的梯形校正系统的硬件和软件实现,说明了该芯片结构、功能及特性,最后提供了校正的效果图. 展开更多
关键词 图像处理 梯形校正 field programmable gate array 锯齿失真
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A New Design Method for Variable Digital Filter Based on Field Programmable Gate Array(FPGA) 被引量:2
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作者 胡文静 仇润鹤 李外云 《Journal of Donghua University(English Edition)》 EI CAS 2012年第2期193-196,共4页
In order to obtain variable characteristics,the digital filter's type,number of taps and coefficients should be changed constantly such that the desired frequency-domain characteristics can be obtained.This paper ... In order to obtain variable characteristics,the digital filter's type,number of taps and coefficients should be changed constantly such that the desired frequency-domain characteristics can be obtained.This paper proposes a method for self-programmable variable digital filter(VDF) design based on field programmable gate array(FPGA).We implement a digital filter system by using custom embedded micro-processor,programmable finite impulse response(P-FIR) macro module,coefficient-loader,clock manager and analog/digital(A/D) or digital/analog(D/A) controller and other modules.The self-programmable VDF can provide the best solution for realization of digital filter algorithms,which are the low-pass,high-pass,band-pass and band-stop filter algorithms with variable frequency domain characteristics.The design examples with minimum 1 to maximum 32 taps FIR filter,based on Modelsim post-routed simulation and onboard running on XUPV5-LX110T,are provided to demonstrate the effectiveness of the proposed method. 展开更多
关键词 variable digital filter(VDF) field programmable gate array(FPga) embedded micro-processor(EMP)
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A novel fuzzy logic direct torque controller for a permanent magnet synchronous motor with a field programmable gate array 被引量:1
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作者 陈永军 《Journal of Chongqing University》 CAS 2008年第3期228-233,共6页
A high-performance digital servo system built on the platform of a field programmable gate array (FPGA),a fully digitized hardware design scheme of a direct torque control (DTC) and a low speed permanent magnet synchr... A high-performance digital servo system built on the platform of a field programmable gate array (FPGA),a fully digitized hardware design scheme of a direct torque control (DTC) and a low speed permanent magnet synchronous motor (PMSM) is proposed. The DTC strategy of PMSM is described with Verilog hardware description language and is employed on-chip FPGA in accordance with the electronic design automation design methodology. Due to large torque ripples in low speed PMSM,the hysteresis controller in a conventional PMSM DTC was replaced by a fuzzy controller. This FPGA scheme integrates the direct torque controller strategy,the time speed measurement algorithm,the fuzzy regulating technique and the space vector pulse width modulation principle. Experimental results indicate the fuzzy controller can provide a controllable speed at 20 r min-1 and torque at 330 N m with satisfactory dynamic and static performance. Furthermore,the results show that this new control strategy decreases the torque ripple drastically and enhances control performance. 展开更多
关键词 fuzzy control direct torque control field programmable gate array permanent magnet synchronous motor
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Synthesis of Nonlinear Control of Switching Topologies of Buck-Boost Converter Using Fuzzy Logic on Field Programmable Gate Array (FPGA) 被引量:1
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作者 Johnson A. Asumadu Vaidhyanathan Jagannathan Arkhom Chachavalnanont 《Journal of Intelligent Learning Systems and Applications》 2010年第1期36-42,共7页
An intelligent fuzzy logic inference pipeline for the control of a dc-dc buck-boost converter was designed and built using a semi-custom VLSI chip. The fuzzy linguistics describing the switching topologies of the conv... An intelligent fuzzy logic inference pipeline for the control of a dc-dc buck-boost converter was designed and built using a semi-custom VLSI chip. The fuzzy linguistics describing the switching topologies of the converter was mapped into a look-up table that was synthesized into a set of Boolean equations. A VLSI chip–a field programmable gate array (FPGA) was used to implement the Boolean equations. Features include the size of RAM chip independent of number of rules in the knowledge base, on-chip fuzzification and defuzzification, faster response with speeds over giga fuzzy logic inferences per sec (FLIPS), and an inexpensive VLSI chip. The key application areas are: 1) on-chip integrated controllers;and 2) on-chip co-integration for entire system of sensors, circuits, controllers, and detectors for building complete instrument systems. 展开更多
关键词 Multi-Fuzzy Logic Controller (MFLC) field programmable gate array (FPga) BUCK-BOOST Converter BOOLEAN Look-Up TABLE CO-INTEGRATION
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Fault Prediction and Diagnosis of Warship Equipment Field Programmable Gate Array Software
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作者 LIU Bojiang YAN Ran +2 位作者 CHAI Haiyan HAN Xinyu TANG Longli 《Journal of Donghua University(English Edition)》 EI CAS 2018年第5期426-429,共4页
In order to solve the current high failure rate of warship equipment field programmable gate array( FPGA) software,fault detection is not timely enough and FPGA detection equipment is expensive and so on. After in-dep... In order to solve the current high failure rate of warship equipment field programmable gate array( FPGA) software,fault detection is not timely enough and FPGA detection equipment is expensive and so on. After in-depth research,this paper proposes a warship equipment FPGA software based on Xilinx integrated development environment( ISE) and ModelSim software.Functional simulation and timing simulation to verify the correctness of the logic design of the FPGA,this method is very convenient to view the signal waveform inside the FPGA program to help FPGA test engineers to achieve FPGA fault prediction and diagnosis. This test method has important engineering significance for the upgrading of warship equipment. 展开更多
关键词 field programmable gate array(FPga) FAULT prediction DIAGNOSIS
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Implimentations of SIMD machine using programmable gate array
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作者 胡铭曾 《Journal of Harbin Institute of Technology(New Series)》 EI CAS 2000年第3期10-13,共4页
Field Programmable Gate Array(FPGA) and Single Instruction Multiple Data(SIMD) processing array share many architecture features. In both architectures, an array is employed to provide high speed computation. In this ... Field Programmable Gate Array(FPGA) and Single Instruction Multiple Data(SIMD) processing array share many architecture features. In both architectures, an array is employed to provide high speed computation. In this paper we show that the implementation of a Single Instruction Multiple Data (SIMD) machine the ABC 90 using the Field Programmable Gate Array (FPGA) is not completely suitable because of its characteristics. The comparison between the programmable gate arrays show that, they have many architectures features in common. Within this framework, we examine the differences and similarities between these array structures and touch upon techniques and lessons which can be done between these architectures in order to choose the appropriate Programmable gate array to implement a general purpose parallel computer. In this paper we introduce the principal of the Dynamically Programmable Date Array(DPGA) which combines the best feature of the FPGA and the SIMD arrays into a single array architecture. By the same way we show that the DPGA is more appropriate then the FPGA for wiring, hardwiring the general purpose parallel computers: SIMD and its implementation. 展开更多
关键词 field programmable gate array Single INSTRUCTION Multiple DATA Dynamically programmable DATA array
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Implementation of Synchronization Technology in Orthogonal Frequency Division Multiplex System Based on Field Programming Gate Array
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作者 YI Qing-ming XIE Sheng-li 《Semiconductor Photonics and Technology》 CAS 2008年第1期32-36,共5页
In this paper,analyzed is the symbol synchronization algorithm in orthogonal frequency division multiplex(OFDM)system,and accomplished are the hardware circuit design of coarse and elaborate synchronization algorithms... In this paper,analyzed is the symbol synchronization algorithm in orthogonal frequency division multiplex(OFDM)system,and accomplished are the hardware circuit design of coarse and elaborate synchronization algorithms.Based on the analysis of coarse and elaborate synchronization algorithms,multiplexed are,the module accumulator,division and output judgement,which can evidently save the hardware resource cost.The analysis of circuit sequence and wave form simulation of the design scheme shows that the proposed method efficiently reduce system resources and power consumption. 展开更多
关键词 orthogonal frequency division multiplex timing synchronization field programmable gate array
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MIXED-GRAINED CMOS FIELD PROGRAMMABLE ANALOG ARRAY FOR SMART SENSORY APPLICATIONS
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作者 Cheng Xiaoyan Yang Haigang +3 位作者 Yin Tao Wu Qisong Zhi Tian Liu Fei 《Journal of Electronics(China)》 2014年第2期129-142,共14页
The drive towards shorter design cycles for analog integrated circuits has given impetus to the development of Field Programmable Analog Arrays(FPAAs),which are the analogue counterparts of Field Programmable Gate Arr... The drive towards shorter design cycles for analog integrated circuits has given impetus to the development of Field Programmable Analog Arrays(FPAAs),which are the analogue counterparts of Field Programmable Gate Arrays(FPGAs).In this paper,we present a new design methodology which using FPAA as a powerful analog front-end processing platform in the smart sensory microsystem.The proposed FPAA contains 16 homogeneous mixed-grained Configurable Analog Blocks(CABs) which house a variety of processing elements especially the proposed fine-grained Core Configurable Amplifiers(CCAs).The high flexible CABs allow the FPAA operating in both continuous-time and discrete-time approaches suitable to support variety of sensors.To reduce the nonideal parasitic effects and save area,the fat-tree interconnection network is adopted in this FPAA.The functionality of this FPAA is demonstrated through embedding of voltage and capacitive sensor signal readout circuits and a configurable band pass filter.The minimal detectable voltage and capacitor achieves 38 uV and 8.3 aF respectively within 100 Hz sensor bandwidth.The power consumption comparison of CCA in three applications shows that the FPAA has high power efficiency.And the simulation results also show that the FPAA has good tolerance with wide PVT variations. 展开更多
关键词 field programmable gate array(FPga) field programmable Analog array(FPAA) Sensor Mixed-grained Configurable Analog Block(CAB) Correlated Double Sampling(CDS)
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FPGA-Based Efficient Programmable Polyphase FIR Filter 被引量:3
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作者 陈禾 熊承欢 +1 位作者 仲顺安 王华 《Journal of Beijing Institute of Technology》 EI CAS 2005年第1期4-8,共5页
The modelling, design and implementation of a high-speed programmable polyphase finite impulse response (FIR) filter with field programmable gate array (FPGA) technology are described. This FIR filter can run automati... The modelling, design and implementation of a high-speed programmable polyphase finite impulse response (FIR) filter with field programmable gate array (FPGA) technology are described. This FIR filter can run automatically according to the programmable configuration word including symmetry/asymmetry, odd/even taps, from 32 taps up to 256 taps. The filter with 12 bit signal and 12 bit coefficient word-length has been realized on a Xilinx VirtexⅡ-v1500 device and operates at the maximum sampling frequency of (160 MHz.) 展开更多
关键词 finite impulse response (FIR) filter POLYPHASE field programmable gate array (FPga)
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Machine learning algorithm partially reconfigured on FPGA for an image edge detection system
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作者 Gracieth Cavalcanti Batista Johnny Oberg +3 位作者 Osamu Saotome Haroldo F.de Campos Velho Elcio Hideiti Shiguemori Ingemar Soderquist 《Journal of Electronic Science and Technology》 EI CAS CSCD 2024年第2期48-68,共21页
Unmanned aerial vehicles(UAVs)have been widely used in military,medical,wireless communications,aerial surveillance,etc.One key topic involving UAVs is pose estimation in autonomous navigation.A standard procedure for... Unmanned aerial vehicles(UAVs)have been widely used in military,medical,wireless communications,aerial surveillance,etc.One key topic involving UAVs is pose estimation in autonomous navigation.A standard procedure for this process is to combine inertial navigation system sensor information with the global navigation satellite system(GNSS)signal.However,some factors can interfere with the GNSS signal,such as ionospheric scintillation,jamming,or spoofing.One alternative method to avoid using the GNSS signal is to apply an image processing approach by matching UAV images with georeferenced images.But a high effort is required for image edge extraction.Here a support vector regression(SVR)model is proposed to reduce this computational load and processing time.The dynamic partial reconfiguration(DPR)of part of the SVR datapath is implemented to accelerate the process,reduce the area,and analyze its granularity by increasing the grain size of the reconfigurable region.Results show that the implementation in hardware is 68 times faster than that in software.This architecture with DPR also facilitates the low power consumption of 4 mW,leading to a reduction of 57%than that without DPR.This is also the lowest power consumption in current machine learning hardware implementations.Besides,the circuitry area is 41 times smaller.SVR with Gaussian kernel shows a success rate of 99.18%and minimum square error of 0.0146 for testing with the planning trajectory.This system is useful for adaptive applications where the user/designer can modify/reconfigure the hardware layout during its application,thus contributing to lower power consumption,smaller hardware area,and shorter execution time. 展开更多
关键词 Dynamic partial reconfiguration(DPR) field programmable gate array(FPga)implementation Image edge detection Support vector regression(SVR) Unmanned aerial vehicle(UAV) pose estimation
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GJB 5000B在FPGA工程中的应用分析
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作者 张鹏 《船舶标准化工程师》 2024年第1期25-28,共4页
为引入软件工程化管理办法对设计开发实践实施管理,结合GJB 5000B体系要求,对现场可编程逻辑门阵列(Field Programmable Gate Array,FPGA)的设计开发流程和GJB 5000B的工程实践要求进行梳理、比对和分析,并提出一套FPGA开发管理在GJB 50... 为引入软件工程化管理办法对设计开发实践实施管理,结合GJB 5000B体系要求,对现场可编程逻辑门阵列(Field Programmable Gate Array,FPGA)的设计开发流程和GJB 5000B的工程实践要求进行梳理、比对和分析,并提出一套FPGA开发管理在GJB 5000B推进实践中的实施办法。研究成果可为GJB 5000B在FPGA工程中的应用提供一定参考。 展开更多
关键词 GJB 5000B 现场可编程逻辑门阵列(field programmable gate array FPga) 项目管理 软件工程化
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Design and verification of an FPGA programmable logic element based on Sense-Switch pFLASH
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作者 Zhengzhou CAO Guozhu LIU +2 位作者 Yanfei ZHANG Yueer SHAN Yuting XU 《Frontiers of Information Technology & Electronic Engineering》 SCIE EI CSCD 2024年第4期485-499,共15页
This paper proposes a kind of programmable logic element(PLE)based on Sense-Switch pFLASH technology.By programming Sense-Switch pFLASH,all three-bit look-up table(LUT3)functions,partial four-bit look-up table(LUT4)fu... This paper proposes a kind of programmable logic element(PLE)based on Sense-Switch pFLASH technology.By programming Sense-Switch pFLASH,all three-bit look-up table(LUT3)functions,partial four-bit look-up table(LUT4)functions,latch functions,and d flip flop(DFF)with enable and reset functions can be realized.Because PLE uses a choice of operational logic(COOL)approach for the operation of logic functions,it allows any logic circuit to be implemented at any ratio of combinatorial logic to register.This intrinsic property makes it close to the basic application specific integrated circuit(ASIC)cell in terms of fine granularity,thus allowing ASIC-like cell-based mappers to apply all their optimization potential.By measuring Sense-Switch pFLASH and PLE circuits,the results show that the“on”state driving current of the Sense-Switch pFLASH is about 245.52μA,and that the“off”state leakage current is about 0.1 pA.The programmable function of PLE works normally.The delay of the typical combinatorial logic operation AND3 is 0.69 ns,and the delay of the sequential logic operation DFF is 0.65 ns,both of which meet the requirements of the design technical index. 展开更多
关键词 field programmable gate array(FPga) programmable logic element(PLE) Boolean logic operation Look-up table Sense-Switch pFLASH Threshold voltage
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一种中值滤波快速系统的FPGA实现 被引量:1
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作者 穆向阳 雷妍 王闻博 《西安石油大学学报(自然科学版)》 CAS 北大核心 2023年第2期128-134,共7页
针对传统焊缝图像滤波实时性差、处理速度慢的问题,提出了一种中值滤波快速系统的FPGA实现方案。首先,在Quartus II软件开发平台中进行系统总体设计,完成了上位机交互模块、地址发生器模块、数据流控制模块和流水卷积中值滤波算法模块... 针对传统焊缝图像滤波实时性差、处理速度慢的问题,提出了一种中值滤波快速系统的FPGA实现方案。首先,在Quartus II软件开发平台中进行系统总体设计,完成了上位机交互模块、地址发生器模块、数据流控制模块和流水卷积中值滤波算法模块的模块化设计,并在数据流控制模块的时序作用下,实现像素分块读取功能及数据的流水线处理功能,进而构建快速滤波卷积核,执行流水中值滤波算法;其次,在Modelsim仿真平台下验证该系统的功能;最后,在MATLAB环境下将本文设计方案与传统的2种中值滤波方案处理的结果进行对比。实验结果表明:以分辨率为600×400的焊缝图像为例,本方案能在保证峰值信噪比的情况下,极大提高处理速度和数据吞吐量,满足图像实时处理的要求。 展开更多
关键词 油气管道 焊缝图像 模块化设计 像素分块读取 流水线处理 快速卷积核 流水中值滤波算法 FPga 快速滤波
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Development of a Wireless Capsule Endoscope System Based on Field Programmable Gate Array
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作者 李四青 刘华 《Journal of Shanghai Jiaotong university(Science)》 EI 2017年第2期156-160,共5页
A new modular and programmable wireless capsule endoscope is presented in this paper. The capsule system consumes low power and has small physical size. A new image compression algorithm is presented in this paper to ... A new modular and programmable wireless capsule endoscope is presented in this paper. The capsule system consumes low power and has small physical size. A new image compression algorithm is presented in this paper to reduce power consumption and silicon area. The compression algorithm includes color space transform, uniform quantization, sub-sampling, differential pulse code modulation (DPCM) and Golomb-Rice code. The algorithm is tested in a field programmable gate array (FPGA) development board, and the final result achieves 80% compression rate at 40 dB peak signal to noise ratio (PSNR). The algorithm has high image compression efficiency and low power consumption, compared to other existing works. The system is composed of the following three parts: image capsule endoscope, portable wireless receiver and host computer software. The software and hardware design of the three parts are disscussed in details. © 2017, Shanghai Jiaotong University and Springer-Verlag Berlin Heidelberg. 展开更多
关键词 capsule endoscope portable receiver compression algorithm field programmable gate array(FPga)
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Implementation of Dynamic Matrix Control on Field Programmable Gate Array
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作者 兰建 李德伟 +1 位作者 杨楠 席裕庚 《Journal of Shanghai Jiaotong university(Science)》 EI 2011年第4期441-446,共6页
High performance computer is often required by model predictive control(MPC) systems due to the heavy online computation burden.To extend MPC to more application cases with low-cost computation facilities, the impleme... High performance computer is often required by model predictive control(MPC) systems due to the heavy online computation burden.To extend MPC to more application cases with low-cost computation facilities, the implementation of MPC controller on field programmable gate array(FPGA) system is studied.For the dynamic matrix control(DMC) algorithm,the main design idea and the implemental strategy of DMC controller are introduced based on a FPGA’s embedded system.The performance tests show that both the computation efficiency and the accuracy of the proposed controller can be satisfied due to the parallel computing capability of FPGA. 展开更多
关键词 model predictive control(MPC) dynamic matrix control(DMC) quadratic programming(QP) active set programmable logic device field programmable gate array(FPga)
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An efficient radix-2 fast Fourier transform processor with ganged butterfly engines on field programmable gate arrays
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作者 Zhen-guo MA Feng YU Rui-feng GE Ze-ke WANG 《Journal of Zhejiang University-Science C(Computers and Electronics)》 SCIE EI 2011年第4期323-329,共7页
We present a novel method to implement the radix-2 fast Fourier transform (FFT) algorithm on field programmable gate arrays (FPGA).The FFT architecture exploits parallelism by having more pipelined units in the stages... We present a novel method to implement the radix-2 fast Fourier transform (FFT) algorithm on field programmable gate arrays (FPGA).The FFT architecture exploits parallelism by having more pipelined units in the stages,and more parallel units within a stage.It has the noticeable advantages of high speed and more efficient resource utilization by employing four ganged butterfly engines (GBEs),and can be well matched to the placement of the resources on the FPGA.We adopt the decimation-infrequency (DIF) radix-2 FFT algorithm and implement the FFT processor on a state-of-the-art FPGA.Experimental results show that the processor can compute 1024-point complex radix-2 FFT in about 11 μs with a clock frequency of 200 MHz. 展开更多
关键词 ganged butterfly engine (GBE) Radix-2 Fast Fourier transform (FFT) field programmable gate array (FPga)
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基于DSP与FPGA的变流器通用控制平台研究 被引量:14
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作者 郭巍 肖遥 孙永佳 《电气传动》 北大核心 2014年第2期22-26,共5页
提出一种基于DSP和现场可编程门阵列(FPGA)双CPU结构的新型变流器控制系统方案,其中DSP完成变流器控制策略的实现,主要包括:最大功率点跟踪、电压电流双闭环控制、低电压穿越控制、通信功能;FPGA完成三相锁相环控制、AD芯片采样控制、SV... 提出一种基于DSP和现场可编程门阵列(FPGA)双CPU结构的新型变流器控制系统方案,其中DSP完成变流器控制策略的实现,主要包括:最大功率点跟踪、电压电流双闭环控制、低电压穿越控制、通信功能;FPGA完成三相锁相环控制、AD芯片采样控制、SVPWM波形控制、逻辑输出控制以及各类故障信号检测与停机保护功能,并采用了基于WIFI模块的风电故障信息传输系统。以双馈风电变流器为模型,设计了双馈风力发电变流器系统,完成了两电平与三电平SVPWM控制算法的FPGA实现。最后在自主研发的1.5 MW,2 MW双馈式变流器样机与光伏逆变器样机上进行了大量实验和长期的现场试运行,验证了控制系统平台的可行性与实用性。 展开更多
关键词 双PWM变流器 矢量控制 数字信号处理器 现场可编程门阵列 digital signal PROCESSOR (DSP) field programmable gate array (FPga)
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SRAM型FPGA单粒子辐照试验系统技术研究 被引量:5
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作者 孙雷 段哲民 +1 位作者 刘增荣 陈雷 《计算机工程与应用》 CSCD 2014年第1期49-52,共4页
单粒子辐射效应严重制约FPGA的空间应用,为提高FPGA在辐射环境中的可靠性,深入研究抗辐射加固FPGA单粒子效应评估方法,设计优化单粒子效应评估方案,开发相应的评估系统,提出基于SRAM时序修正的码流存储比较技术和基于SelectMAP端口配置... 单粒子辐射效应严重制约FPGA的空间应用,为提高FPGA在辐射环境中的可靠性,深入研究抗辐射加固FPGA单粒子效应评估方法,设计优化单粒子效应评估方案,开发相应的评估系统,提出基于SRAM时序修正的码流存储比较技术和基于SelectMAP端口配置回读技术。借助国内高能量大注量率的辐照试验环境,完成FPGA单粒子翻转(SEU)、单粒子闩锁(SEL)和单粒子功能中断(SEFI)等单粒子效应的检测,试验结果表明,该方法可以科学有效地对SRAM型FPGA抗单粒子辐射性能进行评估。 展开更多
关键词 现场可编程门阵列(FPga) 空间辐射 单粒子效应 回读 静态随机存储器(SRAM) field programmable gate array(FPga) Static Random Access Memory(SRAM)
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The use of feld programmable gate array(FPGA)in direct torque control of induction motor
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作者 Y.Srinivasa Kishore BABU G.Tulasi Ram DAS 《控制理论与应用(英文版)》 EI CSCD 2013年第4期642-650,共9页
In this paper, the feasibility of embedding the direct torque control (DTC) of an induction machine into field programmable gate arrays (FPGA) is investigated. DTC of an induction machine is simulated in a MATLAB/... In this paper, the feasibility of embedding the direct torque control (DTC) of an induction machine into field programmable gate arrays (FPGA) is investigated. DTC of an induction machine is simulated in a MATLAB/Simulink environment using a Xilinx system generator. The resulting design has a flexible and modular structure where the designer can customize the hardware blocks by changing the number of inputs, outputs, and algorithm when it is compared to the designs implemented using classical microcontrollers and digital signal processors. With its flexibility, other control algorithms can easily be programmed and embedded into the FPGA. The above system has been implemented on Xilinx Spartan 3A DSP FPGA controller. Simulation and experimentation have been performed to prove the validity of the proposed methodology. 展开更多
关键词 Direct torque control (DTC) Space vector pulse width modulation (SVPWM) System generator (SG) field programmable gate array (FPga) Induction motor (IM)
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阻塞斩波三相交交变频电源的FPGA控制实现 被引量:1
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作者 朱虹 潘小波 +2 位作者 陈玲 关越 张庆丰 《电力系统保护与控制》 EI CSCD 北大核心 2014年第21期116-123,共8页
变频技术是重要的节能技术,所以针对低频或转速不恒定的节能设备,提出了基于FPGA数字控制的三相交交直接变频电源技术。用VHDL语言对主控芯片FPGA编写程序,其输出的高频SPWM信号经驱动电路后作为电源和负载间开关MOSFET的控制信号。MOS... 变频技术是重要的节能技术,所以针对低频或转速不恒定的节能设备,提出了基于FPGA数字控制的三相交交直接变频电源技术。用VHDL语言对主控芯片FPGA编写程序,其输出的高频SPWM信号经驱动电路后作为电源和负载间开关MOSFET的控制信号。MOSFET周期性地部分阻塞电源不能达到负载来改变输出电压的频率,同时在放行的时区斩波来改变输出电压的幅值。基于Matlab仿真平台,对系统进行了建模和仿真,仿真结果验证了该技术的正确性。最后给出了频率为7.14 Hz和2.63 Hz的实验波形,实验结果证明了该技术的可行性。 展开更多
关键词 交交变频 fieldprogrammable gate array(FPga) 斩波 恒压频比 面积等效 占空比 Very—High-Speed Integrated Circuit Hardware Description Language(VHDL)
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