Emerging applications widely use field-programmable gate array(FPGA)prototypes as a tool to verify modern very-large-scale integration(VLSI)circuits,imposing many problems,including routing failure caused by the limit...Emerging applications widely use field-programmable gate array(FPGA)prototypes as a tool to verify modern very-large-scale integration(VLSI)circuits,imposing many problems,including routing failure caused by the limited number of connections among blocks of FPGAs therein.Such a shortage of connections can be alleviated through time-division multiplexing(TDM),by which multiple signals sharing an identical routing channel can be transmitted.In this context,the routing quality dominantly decides the performance of such systems,proposing the requirement of minimizing the signal delay between FPGA pairs.This paper proposes algorithms for the routing problem in a multi-FPGA system with TDM support,aiming to minimize the maximum TDM ratio.The algorithm consists of two major stages:(1)A method is proposed to set the weight of an edge according to how many times it is shared by the routing requirements and consequently to compute a set of approximate minimum Steiner trees.(2)A ratio assignment method based on the edge-demand framework is devised for assigning ratios to the edges respecting the TDM ratio constraints.Experiments were conducted against the public benchmarks to evaluate our proposed approach as compared with all published works,and the results manifest that our method achieves a better TDM ratio in comparison.展开更多
In this paper, the design of a coarse-fine interpolation Time-to-Digital Converter (TDC) is implemented in an ALTERA’s Cyclone FPGA. The carry-select chain performs as the tapped delay line. The Logic Array Block (LA...In this paper, the design of a coarse-fine interpolation Time-to-Digital Converter (TDC) is implemented in an ALTERA’s Cyclone FPGA. The carry-select chain performs as the tapped delay line. The Logic Array Block (LAB) having a propagation delay of 165 ps in the chain is synthesized as delay cell. Coarse counters triggered by the global clock count the more significant bits of the time data. This clock is also fed through the delay line, and LABs create the copies. The replicas are latched by the tested event signal, and the less significant bits are encoded from the latched binary bits. Single-shot resolution of the TDC can be 60 ps. The worst Differential Nonlinearity (DNL) is about 0.2 Least Significant Bit (LSB, 165 ps in this TDC module), and the Integral Nonlinearity (INL) is 0.6 LSB. In comparison with other architectures using the synchronous global clock to sample the taps, this architecture consumed less electric power and logic cells, and is more stable.展开更多
A novel test approach for interconnect resources （IRs） in field programmable gate arrays （FPGA） has been proposed.In the test approach,SBs （switch boxes） of IRs in FPGA has been utilized to test IRs.Furthermore,...A novel test approach for interconnect resources （IRs） in field programmable gate arrays （FPGA） has been proposed.In the test approach,SBs （switch boxes） of IRs in FPGA has been utilized to test IRs.Furthermore,configurable logic blocks （CLBs） in FPGA have also been employed to enhance driving capability and the position of fault IR can be determined by monitoring the IRs associated SBs.As a result,IRs can be scanned maximally with minimum configuration patterns.In the experiment,an in-house developed FPGA test system based on system-on-chip （SoC） hardware/software verification technology has been applied to test XC4000E family of Xilinx.The experiment results revealed that the IRs in FPGA can be tested by 6 test patterns.展开更多
甚高频数据交换系统(Very high frequency Data Exchange System,VDES)作为新一代船舶通信系统,具有广阔的应用前景。由于卫星相对船舶的高速运动,VDES中上行应用特定消息(Application-specific Message,ASM)链路会产生较大的多普勒频移...甚高频数据交换系统(Very high frequency Data Exchange System,VDES)作为新一代船舶通信系统,具有广阔的应用前景。由于卫星相对船舶的高速运动,VDES中上行应用特定消息(Application-specific Message,ASM)链路会产生较大的多普勒频移,在接收端仅依靠已知训练序列估计的频偏等信道参数无法满足正确解调的性能要求。为此提出一种基于判决反馈的解调方法,通过分段解调,缩短每次解调的数据长度,提高解调时对频偏的容忍度,并利用每段解调的结果作为下一段未解调数据的导频,估计出当前数据中的信道参数。仿真结果表明,所提算法相较于无反馈相干解调算法性能大大提升。在上述研究的基础上,在可编程逻辑器件上实现了对ASM无导频上行链路的正确解调。展开更多
基金supported by the Natural Science Foundation of Fujian Province(No.2020J01845)the National Natural Science Foundation of China(Nos.61772005 and 11871280)+1 种基金the Outstanding Youth Innovation Team Project for Universities of Shandong Province(No.2020KJN008)Qinglan Project.
文摘Emerging applications widely use field-programmable gate array(FPGA)prototypes as a tool to verify modern very-large-scale integration(VLSI)circuits,imposing many problems,including routing failure caused by the limited number of connections among blocks of FPGAs therein.Such a shortage of connections can be alleviated through time-division multiplexing(TDM),by which multiple signals sharing an identical routing channel can be transmitted.In this context,the routing quality dominantly decides the performance of such systems,proposing the requirement of minimizing the signal delay between FPGA pairs.This paper proposes algorithms for the routing problem in a multi-FPGA system with TDM support,aiming to minimize the maximum TDM ratio.The algorithm consists of two major stages:(1)A method is proposed to set the weight of an edge according to how many times it is shared by the routing requirements and consequently to compute a set of approximate minimum Steiner trees.(2)A ratio assignment method based on the edge-demand framework is devised for assigning ratios to the edges respecting the TDM ratio constraints.Experiments were conducted against the public benchmarks to evaluate our proposed approach as compared with all published works,and the results manifest that our method achieves a better TDM ratio in comparison.
基金Supported by National Natural Science Foundation of China (No. 10405023)Knowledge Innovation Program of The Chinese Academy of Sciences (KJCX2-YW-N27)
文摘In this paper, the design of a coarse-fine interpolation Time-to-Digital Converter (TDC) is implemented in an ALTERA’s Cyclone FPGA. The carry-select chain performs as the tapped delay line. The Logic Array Block (LAB) having a propagation delay of 165 ps in the chain is synthesized as delay cell. Coarse counters triggered by the global clock count the more significant bits of the time data. This clock is also fed through the delay line, and LABs create the copies. The replicas are latched by the tested event signal, and the less significant bits are encoded from the latched binary bits. Single-shot resolution of the TDC can be 60 ps. The worst Differential Nonlinearity (DNL) is about 0.2 Least Significant Bit (LSB, 165 ps in this TDC module), and the Integral Nonlinearity (INL) is 0.6 LSB. In comparison with other architectures using the synchronous global clock to sample the taps, this architecture consumed less electric power and logic cells, and is more stable.
基金supported by the Key Techniques of FPGA Architecture under Grant No. 9140A08010106QT9201
文摘A novel test approach for interconnect resources （IRs） in field programmable gate arrays （FPGA） has been proposed.In the test approach,SBs （switch boxes） of IRs in FPGA has been utilized to test IRs.Furthermore,configurable logic blocks （CLBs） in FPGA have also been employed to enhance driving capability and the position of fault IR can be determined by monitoring the IRs associated SBs.As a result,IRs can be scanned maximally with minimum configuration patterns.In the experiment,an in-house developed FPGA test system based on system-on-chip （SoC） hardware/software verification technology has been applied to test XC4000E family of Xilinx.The experiment results revealed that the IRs in FPGA can be tested by 6 test patterns.
文摘甚高频数据交换系统(Very high frequency Data Exchange System,VDES)作为新一代船舶通信系统,具有广阔的应用前景。由于卫星相对船舶的高速运动,VDES中上行应用特定消息(Application-specific Message,ASM)链路会产生较大的多普勒频移,在接收端仅依靠已知训练序列估计的频偏等信道参数无法满足正确解调的性能要求。为此提出一种基于判决反馈的解调方法,通过分段解调,缩短每次解调的数据长度,提高解调时对频偏的容忍度,并利用每段解调的结果作为下一段未解调数据的导频,估计出当前数据中的信道参数。仿真结果表明,所提算法相较于无反馈相干解调算法性能大大提升。在上述研究的基础上,在可编程逻辑器件上实现了对ASM无导频上行链路的正确解调。
