Systolic implementation of multiplication over GF(2m) is usually very efficient in area-time complexity,but its latency is usually very large.Thus,two low latency systolic multipliers over GF(2m) based on general irre...Systolic implementation of multiplication over GF(2m) is usually very efficient in area-time complexity,but its latency is usually very large.Thus,two low latency systolic multipliers over GF(2m) based on general irreducible polynomials and irreducible pentanomials are presented.First,a signal flow graph(SFG) is used to represent the algorithm for multiplication over GF(2m).Then,the two low latency systolic structures for multiplications over GF(2m) based on general irreducible polynomials and pentanomials are presented from the SFG by suitable cut-set retiming,respectively.Analysis indicates that the proposed two low latency designs involve at least one-third less area-delay product when compared with the existing designs,To the authors' knowledge,the time-complexity of the structures is the lowest found in literature for systolic GF(2m) multipliers based on general irreducible polynomials and pentanomials.The proposed low latency designs are regular and modular,and therefore they are suitable for many time critical applications.展开更多
We present a new normal basis multiplication scheme using a multiplexer-based algorithm. In this algorithm, the proposed multiplier processes in parallel and has a multiplexer-based structure that uses MUX and XOR gat...We present a new normal basis multiplication scheme using a multiplexer-based algorithm. In this algorithm, the proposed multiplier processes in parallel and has a multiplexer-based structure that uses MUX and XOR gates instead of AND and XOR gates. We show that our multiplier for type-1 and type-2 normal bases saves about 8% and 16%, respectively, in space complexity as compared to existing normal basis multipliers. Finally, the proposed architecture has regular and modular con-figurations and is well suited to VLSI implementations.展开更多
基金Project(61174132) supported by the National Natural Science Foundation of ChinaProject(09JJ6098) supported by the Natural Science Foundation of Hunan Province,China
文摘Systolic implementation of multiplication over GF(2m) is usually very efficient in area-time complexity,but its latency is usually very large.Thus,two low latency systolic multipliers over GF(2m) based on general irreducible polynomials and irreducible pentanomials are presented.First,a signal flow graph(SFG) is used to represent the algorithm for multiplication over GF(2m).Then,the two low latency systolic structures for multiplications over GF(2m) based on general irreducible polynomials and pentanomials are presented from the SFG by suitable cut-set retiming,respectively.Analysis indicates that the proposed two low latency designs involve at least one-third less area-delay product when compared with the existing designs,To the authors' knowledge,the time-complexity of the structures is the lowest found in literature for systolic GF(2m) multipliers based on general irreducible polynomials and pentanomials.The proposed low latency designs are regular and modular,and therefore they are suitable for many time critical applications.
文摘We present a new normal basis multiplication scheme using a multiplexer-based algorithm. In this algorithm, the proposed multiplier processes in parallel and has a multiplexer-based structure that uses MUX and XOR gates instead of AND and XOR gates. We show that our multiplier for type-1 and type-2 normal bases saves about 8% and 16%, respectively, in space complexity as compared to existing normal basis multipliers. Finally, the proposed architecture has regular and modular con-figurations and is well suited to VLSI implementations.
