An efficient method is proposed for the design of finite impulse response(FIR) filter with arbitrary pass band edge,stop band edge frequencies and transition width.The proposed FIR band stop filter is designed using c...An efficient method is proposed for the design of finite impulse response(FIR) filter with arbitrary pass band edge,stop band edge frequencies and transition width.The proposed FIR band stop filter is designed using craziness based particle swarm optimization(CRPSO) approach.Given the filter specifications to be realized,the CRPSO algorithm generates a set of optimal filter coefficients and tries to meet the ideal frequency response characteristics.In this paper,for the given problem,the realizations of the optimal FIR band pass filters of different orders have been performed.The simulation results have been compared with those obtained by the well accepted evolutionary algorithms,such as Parks and McClellan algorithm(PMA),genetic algorithm(GA) and classical particle swarm optimization(PSO).Several numerical design examples justify that the proposed optimal filter design approach using CRPSO outperforms PMA and PSO,not only in the accuracy of the designed filter but also in the convergence speed and solution quality.展开更多
Some fast finite impulse response (FIR) filters use a large number of look-up tables (LUTs) to configure distributed random-access memories (RAMs) and save registers. The distributed RAMs store 2M precomputed sums of ...Some fast finite impulse response (FIR) filters use a large number of look-up tables (LUTs) to configure distributed random-access memories (RAMs) and save registers. The distributed RAMs store 2M precomputed sums of M permuted operands in order to simplify the accumulation, which lays similarity to the solution of Boolean satisfiability (SAT) problem. In this work, a high-speed fault-tolerant FIR digital filter on field programmable gate array (FPGA) is proposed for hardware implementation. A shift register and an RAM are used to arrange the data flow. Generally, an N-tap digital filter only requires N embedded multipliers on FPGA. The better performance is due to high-radix words and low-latency operations. A 32-tap 8-bit FIR digital filter enjoys a throughput of 9.17 MB/s, taking 109 ns to calculate one convolution. In addition, a fault-tolerant scheme by majority logic is used to correct real-time errors within digital filters.展开更多
文摘An efficient method is proposed for the design of finite impulse response(FIR) filter with arbitrary pass band edge,stop band edge frequencies and transition width.The proposed FIR band stop filter is designed using craziness based particle swarm optimization(CRPSO) approach.Given the filter specifications to be realized,the CRPSO algorithm generates a set of optimal filter coefficients and tries to meet the ideal frequency response characteristics.In this paper,for the given problem,the realizations of the optimal FIR band pass filters of different orders have been performed.The simulation results have been compared with those obtained by the well accepted evolutionary algorithms,such as Parks and McClellan algorithm(PMA),genetic algorithm(GA) and classical particle swarm optimization(PSO).Several numerical design examples justify that the proposed optimal filter design approach using CRPSO outperforms PMA and PSO,not only in the accuracy of the designed filter but also in the convergence speed and solution quality.
文摘Some fast finite impulse response (FIR) filters use a large number of look-up tables (LUTs) to configure distributed random-access memories (RAMs) and save registers. The distributed RAMs store 2M precomputed sums of M permuted operands in order to simplify the accumulation, which lays similarity to the solution of Boolean satisfiability (SAT) problem. In this work, a high-speed fault-tolerant FIR digital filter on field programmable gate array (FPGA) is proposed for hardware implementation. A shift register and an RAM are used to arrange the data flow. Generally, an N-tap digital filter only requires N embedded multipliers on FPGA. The better performance is due to high-radix words and low-latency operations. A 32-tap 8-bit FIR digital filter enjoys a throughput of 9.17 MB/s, taking 109 ns to calculate one convolution. In addition, a fault-tolerant scheme by majority logic is used to correct real-time errors within digital filters.
