Low switching loss and increased short-circuit capability split-gate SiC trench MOSFET with p-type pillar

A split-gate SiC trench gate MOSFET with stepped thick oxide, source-connected split-gate(SG), and p-type pillar(ppillar) surrounded thick oxide shielding region(GSDP-TMOS) is investigated by Silvaco TCAD simulations. The sourceconnected SG region and p-pillar shielding region are introduced to form an effective two-level shielding, which reduces the specific gate–drain charge(Q_(gd,sp)) and the saturation current, thus reducing the switching loss and increasing the short-circuit capability. The thick oxide that surrounds a p-pillar shielding region efficiently protects gate oxide from being damaged by peaked electric field, thereby increasing the breakdown voltage(BV). Additionally, because of the high concentration in the n-type drift region, the electrons diffuse rapidly and the specific on-resistance(Ron,sp) becomes smaller.In the end, comparing with the bottom p~+ shielded trench MOSFET(GP-TMOS), the Baliga figure of merit(BFOM,BV~2/R_(on,sp)) is increased by 169.6%, and the high-frequency figure of merit(HF-FOM, R_(on,sp) × Q_(gd,sp)) is improved by310%, respectively.

Remote entangling gate between a quantum dot spin and a transmon qubit mediated by microwave photons

Spin qubits and superconducting qubits are promising candidates for realizing solid-state quantum information processors.Designing a hybrid architecture that combines the advantages of different qubits on the same chip is a highly desirable but challenging goal.Here we propose a hybrid architecture that utilizes a high-impedance SQUID array resonator as a quantum bus,thereby coherently coupling different solid-state qubits.We employ a resonant exchange spin qubit hosted in a triple quantum dot and a superconducting transmon qubit.Since this hybrid system is highly tunable,it can operate in a dispersive regime,where the interaction between the different qubits is mediated by virtual photons.By utilizing such interactions,entangling gate operations between different qubits can be realized in a short time of 30 ns with a fidelity of up to 96.5%under realistic parameter conditions.Further utilizing this interaction,remote entangled state between different qubits can be prepared and is robust to perturbations of various parameters.These results pave the way for exploring efficient fault-tolerant quantum computation on hybrid quantum architecture platforms.

DESIGN OF TWO-PHASE SINUSOIDAL POWER CLOCK AND CLOCKED TRANSMISSION GATE ADIABATIC LOGIC CIRCUIT

First the research is conducted on the design of the two-phase sinusoidal power clock generator in this paper. Then the design of the new adiabatic logic circuit adopting the two-phase sinusoidal power clocks--Clocked Transmission Gate Adiabatic Logic （CTGAL） circuit is presented. This circuit makes use of the clocked transmission gates to sample the input signals, then the output loads are charged and discharged in a fully adiabatic manner by using bootstrapped N-Channel Metal Oxide Semiconductor （NMOS） and Complementary Metal Oxide Semiconductor （CMOS） latch structure. Finally, with the parameters of Taiwan Semiconductor Manufacturing Company （TSMC） 0.25um CMOS device, the transient energy consumption of CTGAL, Bootstrap Charge-Recovery Logic （BCRL） and Pass-transistor Adiabatic Logic （PAL） including their clock generators is simulated. The simulation result indicates that CTGAL circuit has the characteristic of remarkably low energy consumption.

New Design Methodologies for High Speed Low-Voltage 1-Bit CMOS Full Adder Circuits

New methodologies for l-Bit XOR-XNOR full- adder circuits are proposed to improve the speed and power as these circuits are basic building blocks for ALU circuit implementation. This paper presents comparative study of high-speed, low-power and low voltage full adder circuits. Simulation results illustrate the superiority of the proposed adder circuit against the conventional complementary metal-oxide-semiconductor （CMOS）, complementary pass-transistor logic （CPL）, TG, and Hybrid adder circuits in terms of delay, power and power delay product （PDP）. Simulation results reveal that the proposed circuit exhibits lower PDP and is more power efficient and faster when compared with the best available 1-bit full adder circuits. The design is implemented on UMC 0.18 μm process models in Cadence Virtuoso Schematic Composer at 1.8 V single ended supply voltage and simulations are carried out on Spectre S.

THE NEW SUPER-HIGH-SPEED DIGITAL CIRCUIT BASED ON LINEAR AND-OR GATES

The paper reveals the relation between the linear AND-OR gate and the emitter function logic. With theoretic calculation and PSPICE simulation, the paper proves that the linear AND-OR gates can work at super-high-speed and can be multi-cascaded. On the basis of analyzing the high-speed switch units which coordinate with linear AND-OR gates, two kinds of emitter coupled logic circuits are designed. The paper also discusses the design principles of super-high-speed digital circuits, and some examples of combinational and sequential circuits using linear AND-OR gate are given.

Designing a Full Adder Circuit Based on Quasi-Floating Gate

Since in designing the full adder circuits, full adders have been generally taken into account, so as in this paper it has been attempted to represent a full adder cell with a significant efficiency of power, speed and leakage current levels. For this objective, a comparison between five full adder circuits has been provided. Applying floating gate technology and refresh circuits in the full adder cell lead to the reduction of leakage current on the gate node. The simulations were accomplished in this paper, through HSPICE software and 65 nm CMOS technology. The simulation results indicate the considerable efficiency of power consumption, speed and leakage current in the full adder cell rather than other cells.

An Extended Approach for Generating Unitary Matrices for Quantum Circuits

In this paper,we do research on generating unitary matrices for quantum circuits automatically.We consider that quantum circuits are divided into six types,and the unitary operator expressions for each type are offered.Based on this,we propose an algorithm for computing the circuit unitary matrices in detail.Then,for quantum logic circuits composed of quantum logic gates,a faster method to compute unitary matrices of quantum circuits with truth table is introduced as a supplement.Finally,we apply the proposed algorithm to different reversible benchmark circuits based on NCT library(including NOT gate,Controlled-NOT gate,Toffoli gate)and generalized Toffoli(GT)library and provide our experimental results.

Realization of Quantum Circuits in Fock Space

In this letter, by using the method we offered in our paper [L. Ma and Y.D. Zhang, Commun. Theor. Phys.(Beijing, China) 36 (2001) 119], some extended quantum logic gates, such as quantum counter, quantum adder, are studied and their expressions are given. It may be useful for us to study the more complicated quantum logic circuits deeply.

Geometric Phase Gate Based on Both Displacement Operator and Squeezed Operators with a Superconducting Circuit Quantum Electrdynamics

We give the brief review on the related definition of the geometric phase independent of specific physical system based on the displacement opreator and the sqeezed operator, then show how the displacement operator and the squeezed operator can induce the general geometric phase. By means of the displacement operator and the squeezed operator concerning the circuit cavity mode state along a closed path in the phase space, we discuss specifically how to implement a two-qubit geometric phase gate in circuit quantum electrodynamics with both single photon interaction and two-photon interaction between the superconducting qubits and the circuit cavity modes. The experimental feasibility is discussed in detail.

Shortcut-based quantum gates on superconducting qubits in circuit QED

Construction of optimal gate operations is significant for quantum computation.Here an efficient scheme is proposed for performing shortcut-based quantum gates on superconducting qubits in circuit quantum electrodynamics(QED).Two four-level artificial atoms of Cooper-pair box circuits,having sufficient level anharmonicity,are placed in a common quantized field of circuit QED and are driven by individual classical microwaves.Without the effect of cross resonance,one-qubit NOT gate and phase gate in a decoupled atom can be implemented using the invariant-based shortcuts to adiabaticity.With the assistance of cavity bus,a one-step SWAP gate can be obtained within a composite qubit-photon-qubit system by inversely engineering the classical drivings.We further consider the gate realizations by adjusting the microwave fields.With the accessible decoherence rates,the shortcut-based gates have high fidelities.The present strategy could offer a promising route towards fast and robust quantum computation with superconducting circuits experimentally.

Simple Scheme for Realizing the General Conditional Phase Shift Gate and a Simulation of Quantum Fourier Transform in Circuit QED

We propose a theoretical scheme for realizing the general conditional phase shift gate of charge qubits situated in a high-Q superconducting transmission line resonator. The phase shifting angle can be tuned from 0 to 27r by simply adjusting the qubit-resonator detuning and the interaction time. Based on this gate proposal, we give a detailed procedure to implement the three-qubit quantum Fourier transform with circuit quantum eleetrodynamics （QED）. A careful analysis of the decoherence sources shows that the algorithm can be achieved with a high fidelity using current circuit QED techniques.

Design and implementation of high speed TDI CCD timing-driven circuits

The time delay integration charge coupled device(TDI CCD)is the key component in remote sensing systems.The paper analyzes the structure and the working principles of the device according to a customized TDI CCD chip.Employing the special clock resources and large-scale phase locked logic(PLL)in field-programmable gate arrays(FPGA),a timing-driven approach is proposed,using which all timing signals including reset gate,horizontal and vertical timing signals,are implemented in one chip.This not only reduces printed circuit board(PCB)space,but also enhances the portability of the system.By studying and calculating CCD parameters thoroughly,load capacity and power consumption,package,etc,are compared between various candidates chips,and detailed comparison results are also listed in table.Experimental results show that clock generator and driving circuit satisfy the requirements of high speed TDI CCD.

Realization of the iSWAP-like gate among the superconducting qutrits

High-dimensional quantum systems, such as qutrits(quantum three-level systems), have multiple accessible energy levels beyond the two-level qubits. Therefore, qutrits can offer a larger state space to improve the efficiency of quantum computation. Here, we demonstrate a high-fidelity iSWAP-like gate operation on a frequency-tunable superconducting qutrits system. The superconducting quantum system consists of two qutrits that are coupled via a resonator with fixed qutrit-resonator coupling strengths. Through designing the frequency pulse profile and optimizing the parameter values,the gate error can be suppressed below 1.5 × 10^(-3). To bear out the feasibility of the proposal, we have conducted our study with experimentally accessible parameters. As the resonator can mediate the interaction between the irrelevant qutrits, the presented approach can also be used to couple multiple qutrits together, providing a good platform for quantum information processing.

基于相关性分离的逻辑电路敏感门定位算法

随着CMOS器件特征尺寸进入纳米量级,因高能粒子辐射等造成的电路失效问题日益严重,给电路可靠性带来严峻挑战。现阶段,准确评估集成电路可靠性,并以此为依据对电路进行容错加固,以提高电路系统可靠性变得刻不容缓。然而,由于逻辑电路中存在大量扇出重汇聚结构,由此引发的信号相关性导致可靠性评估与敏感单元定位面临困难。该文提出一种基于相关性分离的逻辑电路敏感门定位算法。先将电路划分为多个独立电路结构(ICS);以ICS为基本单元分析故障传播及信号相关性影响;再利用相关性分离后的电路模块和反向搜索算法精准定位逻辑电路敏感门单元;最后综合考虑面向输入向量空间的敏感门定位及针对性容错加固。实验结果表明,所提算法能准确、高效地定位逻辑电路敏感单元,适用于大规模及超大规模电路的可靠性评估与高效容错设计。

高压大功率SiC MOSFETs短路保护方法

碳化硅(SiC)MOSFETs短路承受能力弱,研究其短路保护方法成为保障电力电子设备安全运行的重要课题。现有方法大多围绕低压小功率SiC MOSFETs,然而随着电压和功率等级的提升,器件特性有所差异,直接套用以往设计难以实现高压大功率SiC MOSFETs的快速、可靠保护。该文首先详细研究了几种常用短路检测方法;其次基于高压大功率SiC MOSFETs器件特性,深入对比分析了不同短路检测方法的适用性,提出一种阻容式漏源极电压检测和栅极电荷检测相结合的短路保护方法;最后搭建了实验平台验证所提方法的可行性。结果表明,提出的方法在硬开关短路故障(hard switching fault,HSF)下,保护响应时间缩短了1.4μs,短路能量降低了62.5%;且能可靠识别负载短路故障(fault under load,FUL)。

一种窄脉冲信号峰值电压检测电路设计

SiCMOSFET器件栅极峰值电流可以表征器件结温,但是栅极峰值电流信号上升下降速度快、维持时间短,给峰值电压信号检测电路设计带来了挑战。此处提出了一种基于两级峰值采样保持电路的窄脉冲峰值电压检测电路,其具有采集精度高、保持时间长等优点。首先介绍了峰值检测原理以及两级峰值检测原理,然后给出了详细的电路参数选型,最后,利用仿真和实验对此处所提峰值电流检测电路进行了验证。结果表明,所提峰值检测电路检测误差小于1.1%,电压下垂速率为0.55μV/μs。

一种MCT门量子可逆线路分解与优化方法

为提高可逆线路中MCT门的分解和优化效率,提出了一种MCT门的优化分解方法,根据该方法得出MCT分解模板并验证了正确性。基于该模板给出了相应的分解与优化算法,算法对MCT门分解出的Toffoli线路进行分类,使用优化分解模板将其分解为NCV线路。该算法的时间复杂度为O(m),优于传统算法的复杂度O(m2)。通过对控制位m∈{3,10}的MCT门与Benchmark可逆线路的实验,验证了该算法优化和分解的有效性。

超高重频卫星激光测距时序电路实现及应用

高重频卫星激光测距(Satellite Laser Ranging,SLR)具有精度高、捕获快、观测数据量大、可靠性高等优势。但随着重复频率提升至百千赫兹以上,现有测量时序电路无法达到系统运行处理速度和实时后向散射规避等要求。本文提出超高重频卫星激光测距时序电路设计方法,采用FPGA代替控制计算机进行门控距离实时计算,精确产生门控信号控制探测器开启,并使用了收发交替的方式实时调整激光点火信号以规避后向散射干扰。能够自主完成激光测距中距离门控输出时刻的计算、存储和信号输出,最高工作频率大于500 kHz,满足百千赫兹超高频率测距的要求。该系统已成功应用于上海天文台100 kHz重复率SLR,标准点精度突破200μm,验证了基于FPGA的测距时序电路的正确性和潜力。该电路设计简单、分辨率高、上位机交互方便,为百kHz~MHz的超高重频SLR系统时序控制电路设计提供有效解决方案。

单光子雪崩二极管SPICE仿真模型的建立和应用

单光子雪崩二极管(SPAD)作为一种高效的光子探测器件被广泛应用于量子通信和三维成像等领域。在Cadence中建立了一个SPAD的Spice模型,通过Verilog-A语言,采用两个e指数函数的组合,以连续函数的方式描述了SPAD在盖革模式区等效电阻的动态变化。这两个e指数函数分别体现了高阻区和低阻区的等效电阻特性,解决了分段电阻模型仿真不收敛的问题。该Spice模型模拟了SPAD器件在“接收光子-雪崩产生脉冲-淬灭-复位”工作过程中的动态特性和SPAD从正偏到二次击穿的静态I-V特性。将其应用到4种不同淬灭电路的仿真中,验证了该模型的有效性和稳定性。

感应加热电源的IGBT驱动保护系统设计

为提高感应加热电源的绝缘栅双极型晶体管(IGBT)信号源与保护电路的稳定性,设计了应用于工业化低频大功率感应加热电源设备的IGBT驱动保护系统。系统整体采用复杂可编程逻辑器件(CPLD)+数字信号处理(DSP)协同工作方案,由低频正弦脉冲宽度调制(SPWM)技术控制,以脉冲变压器2ED300C17-S为IGBT保护电路的核心,设计了IGBT故障处理电路、退饱和检测电路与有源钳位电路等多种保护电路。对系统进行理论分析与Matlab/Simulink仿真,搭建了实物测试平台。试验结果表明,当工件加热到900℃时,逆变器输出功率参数与负载端功率参数达到大功率感应加热电源要求,且信号源输出稳定性高、保护电路响应时间快。该设计为相关工业化应用提供技术支持。