Organic field-effect transistor floating-gate memory using polysilicon as charge trapping layer

In this study,we present an organic field-effect transistor floating-gate memory using polysilicon(poly-Si)as a charge trapping layer.The memory device is fabricated on a N^+-Si/SiO2 substrate.Poly-Si,polymethylmethacrylate,and pentacene are used as a floating-gate layer,tunneling layer,and active layer,respectively.The device shows bidirectional storage characteristics under the action of programming/erasing(P/E)operation due to the supplied electrons and holes in the channel and the bidirectional charge trapping characteristic of the poly-Si floating-gate.The carrier mobility and switching current ratio(Ion/Ioff ratio)of the device with a tunneling layer thickness of 85 nm are 0.01 cm^2·V^-1·s^-1 and 102,respectively.A large memory window of 9.28 V can be obtained under a P/E voltage of±60 V.

Floating-gate photosensitive synaptic transistors with tunable functions for neuromorphic computing

Synaptic devices that merge memory and processing functions into one unit have broad application potentials in neuromorphic computing, soft robots, and humanmachine interfaces. However, most previously reported synaptic devices exhibit fixed performance once been fabricated,which limits their application in diverse scenarios. Here, we report floating-gate photosensitive synaptic transistors with charge-trapping perovskite quantum dots(PQDs) and atomic layer deposited(ALD) Al_(2)O_(3) tunneling layers, which exhibit typical synaptic behaviors including excitatory postsynaptic current(EPSC), pair-pulse facilitation and dynamic filtering characteristics under both electrical or optical signal stimulation. Further, the combination of the high-quality Al2O3 tuning layer and highly photosensitive PQDs charge-trapping layer provides the devices with extensively tunable synaptic performance under optical and electrical co-modulation. Applying light during electrical modulation can significantly improve both the synaptic weight changes and the nonlinearity of weight updates, while the memory effect under light modulation can be obviously adjusted by the gate voltage.The pattern learning and forgetting processes for "0" and "1"with different synaptic weights and memory times are further demonstrated in the device array. Overall, this work provides synaptic devices with tunable functions for building complex and robust artificial neural networks.

Reliability of High Speed Ultra Low Voltage Differential CMOS Logic

In this paper, we present a solution to the ultra low voltage inverter by adding a keeper transistor in order to make the semi-floating-gate more stable and to reduce the current dissipation. Moreover, we also present a differential ULV inverter and elaborate on the reliability and fault tolerance of the gate. The differential ULV gate compared to both a former ULV gate and standard CMOS are given. The results are obtained through Monte-Carlo simulations.