Based on the minimum settling time （MST） theory and step-response analysis of the second order system in active switched capacitor （SC） networks, a novel clock feedthrough frequency compensation （CFFC） method fo...Based on the minimum settling time （MST） theory and step-response analysis of the second order system in active switched capacitor （SC） networks, a novel clock feedthrough frequency compensation （CFFC） method for a folded-cascode OTA is proposed. The damping factor r/is adjusted by using MOS capacitors to introduce clock feedthrough so that the OTA can obtain the MST state and thus achieve fast settling. Research results indicate that the settling time of the compensated OTA is reduced by 22.7% ;as the capacitor load varies from 0.5 to 2.5pF,the improved settling time increases approximately linearly from 3.62 to 4.46ns： for VGA application, fast settling can also be achieved by modifying the MOS capacitor value accordingly when the closed loop gain of the compensated OTA varies.展开更多
A new configuration of Bulk-Driven Folded-Cascode (BDFC) amplifier is presented in this paper. Due to this modifying, significant improvement in differential DC-Gain (more than 11 dB) is achieved in compare to the con...A new configuration of Bulk-Driven Folded-Cascode (BDFC) amplifier is presented in this paper. Due to this modifying, significant improvement in differential DC-Gain (more than 11 dB) is achieved in compare to the conventional structure. Settling behavior of proposed amplifier is also improved and accuracy more than 8 bit for 500 mV voltage swing is obtained. Simulation results using HSPICE Environment are included which validate the theoretical analysis. The amplifier is designed using standard 0.18 μm CMOS triple-well (level 49) process with supply voltage of 1.2 V. The correct functionality of this configuration is verified from –50℃ to 100℃.展开更多
The folded-cascode structure is used to realize the low-voltage low-power consumption mixer, whose performance parameters have big influence on the navigation radio receiver＇s performance. Adopting the folded-cascode...The folded-cascode structure is used to realize the low-voltage low-power consumption mixer, whose performance parameters have big influence on the navigation radio receiver＇s performance. Adopting the folded-cascode structure, the folded-cascode mixer （FCM） has a lower power supply voltage of 1.2 V and realizes the design trade-offs among the high transconductance, high linearity and low noise. The difficulties of realizing the trade-offs between the linearity and noise performance, the linearity and conversion gain, the conversion gain and noise performance are reduced. Fabricated in an radio frequency （RF） 0.18 μm CMOS process, the FCM has an active area of about 200 μm ×150 μm and consumes approximate 3.9 mW. The test results show that the FCM features a conversion gain （Gc） of some 14.5 dB, an input 1 dB compression point （Pin-1dB） of almost -13 dBm and a dual sideband （DSB） noise figure of around 12 dB. The FCM can be applied to the navigation radio receivers and electronic systems for aviation and aerospace or other related fields.展开更多
At high speeds and high resolution, the Pipeline ADCs are becoming popular. The options of different stage resolutions in Pipelined ADCs and their effect on speed, power dissipation, linearity and area are discussed i...At high speeds and high resolution, the Pipeline ADCs are becoming popular. The options of different stage resolutions in Pipelined ADCs and their effect on speed, power dissipation, linearity and area are discussed in this paper. The basic building blocks viz. Op-Amp Sample and Hold circuit, sub converter, D/A Converter and residue amplifier used in every stage is assumed to be identical. The sub converters are implemented using flash architectures. The paper implements a 10-bit 50 Mega Samples/Sec Pipelined A/D Converter using 1, 1.5, 2, 3, 4 and 5 bits/stage conversion techniques and discusses about its impact on speed, power, area, and linearity. The design implementation uses 0.18 μm CMOS technology and a 3.3 V power supply. The paper concludes stating that a resolution of 2 bits/stage is optimum for a Pipelined ADC and to reduce the design complexity, we may go up to 3 bits/stage.展开更多
文摘Based on the minimum settling time （MST） theory and step-response analysis of the second order system in active switched capacitor （SC） networks, a novel clock feedthrough frequency compensation （CFFC） method for a folded-cascode OTA is proposed. The damping factor r/is adjusted by using MOS capacitors to introduce clock feedthrough so that the OTA can obtain the MST state and thus achieve fast settling. Research results indicate that the settling time of the compensated OTA is reduced by 22.7% ;as the capacitor load varies from 0.5 to 2.5pF,the improved settling time increases approximately linearly from 3.62 to 4.46ns： for VGA application, fast settling can also be achieved by modifying the MOS capacitor value accordingly when the closed loop gain of the compensated OTA varies.
文摘A new configuration of Bulk-Driven Folded-Cascode (BDFC) amplifier is presented in this paper. Due to this modifying, significant improvement in differential DC-Gain (more than 11 dB) is achieved in compare to the conventional structure. Settling behavior of proposed amplifier is also improved and accuracy more than 8 bit for 500 mV voltage swing is obtained. Simulation results using HSPICE Environment are included which validate the theoretical analysis. The amplifier is designed using standard 0.18 μm CMOS triple-well (level 49) process with supply voltage of 1.2 V. The correct functionality of this configuration is verified from –50℃ to 100℃.
文摘The folded-cascode structure is used to realize the low-voltage low-power consumption mixer, whose performance parameters have big influence on the navigation radio receiver＇s performance. Adopting the folded-cascode structure, the folded-cascode mixer （FCM） has a lower power supply voltage of 1.2 V and realizes the design trade-offs among the high transconductance, high linearity and low noise. The difficulties of realizing the trade-offs between the linearity and noise performance, the linearity and conversion gain, the conversion gain and noise performance are reduced. Fabricated in an radio frequency （RF） 0.18 μm CMOS process, the FCM has an active area of about 200 μm ×150 μm and consumes approximate 3.9 mW. The test results show that the FCM features a conversion gain （Gc） of some 14.5 dB, an input 1 dB compression point （Pin-1dB） of almost -13 dBm and a dual sideband （DSB） noise figure of around 12 dB. The FCM can be applied to the navigation radio receivers and electronic systems for aviation and aerospace or other related fields.
文摘At high speeds and high resolution, the Pipeline ADCs are becoming popular. The options of different stage resolutions in Pipelined ADCs and their effect on speed, power dissipation, linearity and area are discussed in this paper. The basic building blocks viz. Op-Amp Sample and Hold circuit, sub converter, D/A Converter and residue amplifier used in every stage is assumed to be identical. The sub converters are implemented using flash architectures. The paper implements a 10-bit 50 Mega Samples/Sec Pipelined A/D Converter using 1, 1.5, 2, 3, 4 and 5 bits/stage conversion techniques and discusses about its impact on speed, power, area, and linearity. The design implementation uses 0.18 μm CMOS technology and a 3.3 V power supply. The paper concludes stating that a resolution of 2 bits/stage is optimum for a Pipelined ADC and to reduce the design complexity, we may go up to 3 bits/stage.
