A single-channel 2 GS/s 8-bit analog-to-digital converter in 90 nm CMOS process technology is pre- sented. It utilizes cascade folding architecture, which incorporates an additional inter-stage sample-and-hold ampli- ...A single-channel 2 GS/s 8-bit analog-to-digital converter in 90 nm CMOS process technology is pre- sented. It utilizes cascade folding architecture, which incorporates an additional inter-stage sample-and-hold ampli- fier between the folding circuits to enhance the quantization time. It also uses the foreground on-chip digital-assisted calibration circuit to improve the linearity of the circuit. The post simulation results demonstrate that it has a dif- ferential nonlinearity 〈 4-0.3 LSB and an integral nonlinearity 〈 ±0.25 LSB at the Nyquist frequency. Moreover, 7.338 effective numbers of bits can be achieved at 2 GSPS. The whole chip area is 0.88 × 0.88 mm2 with the pad. It consumes 210 mW from a 1.2 V single supply.展开更多
基金Project supported by National Basic Research Program of China(No.2010CB327400)the Natural Science Foundation of Shandong Province,China(No.ZR2013FL007)
文摘A single-channel 2 GS/s 8-bit analog-to-digital converter in 90 nm CMOS process technology is pre- sented. It utilizes cascade folding architecture, which incorporates an additional inter-stage sample-and-hold ampli- fier between the folding circuits to enhance the quantization time. It also uses the foreground on-chip digital-assisted calibration circuit to improve the linearity of the circuit. The post simulation results demonstrate that it has a dif- ferential nonlinearity 〈 4-0.3 LSB and an integral nonlinearity 〈 ±0.25 LSB at the Nyquist frequency. Moreover, 7.338 effective numbers of bits can be achieved at 2 GSPS. The whole chip area is 0.88 × 0.88 mm2 with the pad. It consumes 210 mW from a 1.2 V single supply.
