Raman lasers are essential in atomic physics,and the development of portable devices has posed requirements for time-division multiplexing of Raman lasers.We demonstrate an innovative gigahertz frequency hopping appro...Raman lasers are essential in atomic physics,and the development of portable devices has posed requirements for time-division multiplexing of Raman lasers.We demonstrate an innovative gigahertz frequency hopping approach of a slave Raman laser within an optical phase-locked loop(OPLL),which finds practical application in an atomic gravimeter,where the OPLL frequently switches between near-resonance lasers and significantly detuned Raman lasers.The method merges the advantages of rapid and extensive frequency hopping with the OPLL’s inherent low phase noise,and exhibits a versatile range of applications in compact laser systems,promising advancements in portable instruments.展开更多
In BEPC Ⅱ(Upgrade of Beijing Electron-Position Collider),multi-bunches and high current operation mode is usually used.Due to the influence of high frequency cavity structure or resistance impedance,the beam will be ...In BEPC Ⅱ(Upgrade of Beijing Electron-Position Collider),multi-bunches and high current operation mode is usually used.Due to the influence of high frequency cavity structure or resistance impedance,the beam will be unstable.If the beam is unstable,the luminosity and brightness of the accelerator will be decreased.In order to improve the beam current and brightness of accelerator and the collider luminosity,the beam feedback system is needed to suppress the instability.The trifold frequency multiplier by using triode is simple to operate,and it has good performance.In the experiments,the 500MHz signal was passed through the Triode Frequency Multiplier to get the 1.5GHz signal,and its output amplitude stability is 1.7mV,and its synchronization stability is 3.46ps compared with the 500MHz input signal.展开更多
A fully integrated integer-N frequency synthesizer is implemented.The synthesizer is designed for low intermediate frequency (IF)ZigBee transceiver applications.Techniques used to make the loop bandwidth constant ac...A fully integrated integer-N frequency synthesizer is implemented.The synthesizer is designed for low intermediate frequency (IF)ZigBee transceiver applications.Techniques used to make the loop bandwidth constant across the whole output frequency range of the voltage controlled oscillator(VCO)are adopted to maintain phase noise optimization and loop stability.In-phase and quadrature(IQ)signals are generated by a 1/2 frequency divider at the output of the VCO.The synthesizer is fabricated in 0.18 μm radio frequency(RF) complementary metal oxide semiconductor transistor (CMOS)technology.The chip area is 1.7 mm2.The synthesizer is measured on wafer.It consumes totally 28.8 mW excluding output buffers from a supply voltage of 1.8 V.The measured phase noise is -110 and -122 dBc/Hz at the offset of 1 and 3 MHz from a 2.405 GHz carrier,respectively.The measured reference spur at a 2 MHz offset from a 2.405 GHz carrier is-48.2 dBc.The measured setting time of the synthesizer is about 160 μs.展开更多
The design procedure of an 1-GHz phase-locked loop (PLL)-based frequency synthesizer used in IEEE 1394b physical (PHY) system is presented in this paper. The PLL's loop dynamics are analyzed in depth and theoreti...The design procedure of an 1-GHz phase-locked loop (PLL)-based frequency synthesizer used in IEEE 1394b physical (PHY) system is presented in this paper. The PLL's loop dynamics are analyzed in depth and theoretical relationships between all loop parameters are clearly described. All the parameters are derived and verified by Verilog-A model, which ensures the accuracy and efficiency of the circuit design and simulation. A 4-stage ring oscillator is employed to generate 1-GHz oscillation frequency and is divided into low frequency clocks by a feedback divider. The architecture is a third-order, type-2 charge pump PLL. The simulated settling time is less than 4μs. The RMS value of period jitter of the PLL's output is 2.1 ps. The PLL core occupies an area of 0.12 mm2, one fourth of which is occupied by the MiM loop capacitors. The total current consumption of the chip is 16.5 mA. The chip has been sent for fabrication in 0.13 μm complementary metal oxide semiconductor (CMOS) technology.展开更多
In this paper, we demonstrate a carrier envelope phase-stabilized Yb-doped fiber frequency comb seeding by a nonlinear-polarization-evolution(NPE) mode-locked laser at a repetition rate of 60 MHz with a pulse durati...In this paper, we demonstrate a carrier envelope phase-stabilized Yb-doped fiber frequency comb seeding by a nonlinear-polarization-evolution(NPE) mode-locked laser at a repetition rate of 60 MHz with a pulse duration of 191 fs.The pump-induced carrier envelope offset frequency( f0) nonlinear tuning is discussed and further explained by the spectrum shift of the laser pulse. Through the environmental noise suppression, the drift of the free-running f0 is reduced down to less than 3 MHz within an hour. By feedback control on the pump power with a self-made phase-lock loop(PLL)electronics the carrier envelope offset frequency is well phase-locked with a frequency jitter of 85 m Hz within an hour.展开更多
A bandwidth microwave second harmonic generator is successfully designed using composite right/left-handed non- linear transmission lines (CRLH NLTLs) in a GaAs monolithic microwave integrated circuit (MMIC) techn...A bandwidth microwave second harmonic generator is successfully designed using composite right/left-handed non- linear transmission lines (CRLH NLTLs) in a GaAs monolithic microwave integrated circuit (MMIC) technology. The structure parameters of CRLH NLTLs, e.g. host transmission line, rectangular spiral inductor, and nonlinear capacitor, have a great impact on the second harmonic performance enhancement in terms of second harmonic frequency, output power, and conversion efficiency. It has been experimentally demonstrated that the second harmonic frequency is deter- mined by the anomalous dispersion of CRLH NLTLs and can be significantly improved by effectively adjusting these structure parameters. A good agreement between the measured and simulated second harmonic performances of Ka-band CRLH NLTLs frequency multipliers is successfully achieved, which further validates the design approach of frequency multipliers on CRLH NLTLs and indicates the potentials of CRLH NLTLs in terms of the generation of microwave and millimeter-wave signal source.展开更多
A fully integrated frequency synthesizer with low jitter and low power consumption in 0.18 μm CMOS (complementary metal-oxide semiconductor) technology is proposed in this paper.The frequency synthesizer uses a novel...A fully integrated frequency synthesizer with low jitter and low power consumption in 0.18 μm CMOS (complementary metal-oxide semiconductor) technology is proposed in this paper.The frequency synthesizer uses a novel single-end gain-boosting charge pump, a differential coupled voltage controlled oscillator (VCO) and a dynamic logic phase/frequency detecor (PFD) to acquire low output jitter.The output frequency range of the frequency synthesizer is up to 1 200 MHz to 1 400 MHz for GPS (global position system) application.The post simulation results show that the phase noise of VCO is only 127.1 dBc/Hz at a 1 MHz offset and the Vp-p jitter of the frequency synthesizer output clock is 13.65 ps.The power consumption of the frequency synthesizer not including the divider is 4.8 mW for 1.8 V supply and it occupies a 0.8 mm×0.7 mm chip area.展开更多
High quality speed information is one of the key issues in machine sensorless drives,which often requires proper filtering of the estimated speed.This paper comparatively studies typical low-pass filters(LPF)and phase...High quality speed information is one of the key issues in machine sensorless drives,which often requires proper filtering of the estimated speed.This paper comparatively studies typical low-pass filters(LPF)and phase-locked loop(PLL)type filters with respect to ramp speed reference tracking and steady-state performances,as well as the achievement of adaptive cutoff frequency control.An improved LPF-based filter structure with no ramping and steady-state errors caused by filter parameter quantization effects is proposed,which is suitable for applying LPF for sensorless drives of AC machines,especially when fixed-point digital signal processor is selected e.g.in mass production.Furthermore,the potential of adopting PLL for speed filtering is explored.It is demonstrated that PLL type filters can well maintain the advantages offered by the improved LPF.Moreover,it is found that the PLL type filters exhibit almost linear relationship between the cutoff frequency of the PLL filter and its proportional-integral(PI)gains,which can ease the realization of speed filters with adaptive cutoff frequency for improving the speed transient performance.The proposed filters are verified experimentally.The PLL type filter with adaptive cutoff frequency can provide satisfactory performances under various operating conditions and is therefore recommended.展开更多
The phase-locking process is studied for high-power gyrotron oscillator driven by an external signal. The phase-locking nonlinear differential equations are derived, and the condition of phase-locking is shown and ana...The phase-locking process is studied for high-power gyrotron oscillator driven by an external signal. The phase-locking nonlinear differential equations are derived, and the condition of phase-locking is shown and analyzed. The phase-locking signal can be introduced after gyrotron oscillates into saturation or before it. Two different ways of inputting signal make markable influence on the phase-locking process, this phenomenon is discussed. In this paper, the numerical calculations and analysis are given for gyrotron TE13 mode.展开更多
A control strategy of frequency self-adaptation without phase-locked loop(PLL)underαβstationary reference frame(αβ-SRF)for a VSC-HVDC system is presented to improve the operational performance of the system under ...A control strategy of frequency self-adaptation without phase-locked loop(PLL)underαβstationary reference frame(αβ-SRF)for a VSC-HVDC system is presented to improve the operational performance of the system under severe harmonic distortion conditions.The control strategy helps to eliminate the cross-coupling under dq synchronous reference frame(dq-SRF),and is achieved through two key technologies:1)positive phase sequence(PPS)and negative phase sequence(NPS)fundamental components are extracted from the AC grid voltage with an improved multiple complex coefficient filter(IMCF),and 2)grid instantaneous frequency is rapidly and precisely tracked using a frequency self-adaptation tracking algorithm(FATA)without PLL.The proposed strategy is applied to a point-to-point VSCHVDC system and validated by means of simulations.The results are compared to those with the traditional vector control strategy under dq-SRF.Simulation results illustrate that the proposed strategy results in better system performance than that with the traditional strategy in terms of harmonic suppression under normal and severe operating conditions of the AC system.展开更多
Natural frequencies for multilayer plates are calculated by mixed finite element method. The main object of this paper is to use the mixed model for multilayer plates, analyzing each layer as an isolated plate, where ...Natural frequencies for multilayer plates are calculated by mixed finite element method. The main object of this paper is to use the mixed model for multilayer plates, analyzing each layer as an isolated plate, where the continuity of displacements is achieved by Lagrange multipliers (representing static variables). This procedure allows us to work with any model for single plate (so as to ensure the proper behavior of each layer), and the complexity of the multilayer system is avoided by ensuring the condition of displacements by the Lagrange multipliers (static variables). The plate is discretized by finite element modeling based on a primary hybrid model, where the domain is divided by quadrilateral, both for the displacement field and static variables. This mixed element for plates was implemented and several examples of vibrations have been verified successfully by the results obtained by other methods in the literature.展开更多
From the point of view of system design, a configuration of fiber-optic interferomet- ric hydrophone array and its modulation and demodulation approach using frequncy division multiplexing technique based on Phase Gen...From the point of view of system design, a configuration of fiber-optic interferomet- ric hydrophone array and its modulation and demodulation approach using frequncy division multiplexing technique based on Phase Generated Carrier (PGC) is introduced. And the em- phasis on demonstrating the relationship among the number of units N, the detectable signal amplitude D and the detectable frequency ws through analyzing the frequency spectrum of the output signal of the J × K array and the key factor which restricts N, D, Ws for increasing are presented. The maximum phare shift and the law of its variation according to frequency are specially analyzed. The results induced from some relative theory were verified by experiments.展开更多
太赫兹源的输出功率是限制太赫兹技术远距离应用的重要参数。为了实现高效的太赫兹倍频器,基于高频特性下肖特基二极管的有源区电气模型建模方法,利用指标参数不同的两种肖特基二极管,研制出了两种170 GHz平衡式倍频器。所采用的肖特基...太赫兹源的输出功率是限制太赫兹技术远距离应用的重要参数。为了实现高效的太赫兹倍频器,基于高频特性下肖特基二极管的有源区电气模型建模方法,利用指标参数不同的两种肖特基二极管,研制出了两种170 GHz平衡式倍频器。所采用的肖特基二极管有源结区模型完善地考虑了二极管IV特性,载流子饱和速率限制,直流串联电阻以及趋肤效应等特性。通过对两种倍频器仿真结果进行对比,完备地分析了二极管主要指标参数对倍频器性能的影响。最后测试结果显示两种平衡式170 GHz倍频器在155~178 GHz工作带宽内的最高倍频效率分别大于11%和24%,最高输出功率分别大于15 m W和25 m W。从仿真和测试结果表示,采用的肖特基二极管建模方法和平衡式倍频器结构适用于研制高效的太赫兹倍频器。展开更多
In order to effectively control the working state of the gyroscope in drive mode, the drive characteristics of the micro electromechanical system (MEMS) gyroscope are analyzed in principle. A novel drive circuit for...In order to effectively control the working state of the gyroscope in drive mode, the drive characteristics of the micro electromechanical system (MEMS) gyroscope are analyzed in principle. A novel drive circuit for the MEMS gyroscope in digital closed-loop control is proposed, which utilizes a digital phase-locked loop (PLL) in frequency control and an automatic gain control (AGC) method in amplitude control. A digital processing circuit with a field programmable gate array (FPGA) is designed and the experiments are carried out. The results indicate that when the temperature changes, the drive frequency can automatically track the resonant frequency of gyroscope in drive mode and that of the oscillating amplitude holds at a set value. And at room temperature, the relative deviation of the drive frequency is 0.624 ×10^-6 and the oscillating amplitude is 8.0 ×10^-6, which are 0. 094% and 18. 39% of the analog control program, respectively. Therefore, the control solution of the digital PLL in frequency and the AGC in amplitude is feasible.展开更多
基金Project supported by the National Key Research and Development Program of China(Grant Nos.2021YFA0718300 and 2021YFA1400900)the National Natural Science Foundation of China(Grant Nos.11920101004,11934002,and 92365208)+1 种基金Science and Technology Major Project of Shanxi(Grant No.202101030201022)Space Application System of China Manned Space Program.
文摘Raman lasers are essential in atomic physics,and the development of portable devices has posed requirements for time-division multiplexing of Raman lasers.We demonstrate an innovative gigahertz frequency hopping approach of a slave Raman laser within an optical phase-locked loop(OPLL),which finds practical application in an atomic gravimeter,where the OPLL frequently switches between near-resonance lasers and significantly detuned Raman lasers.The method merges the advantages of rapid and extensive frequency hopping with the OPLL’s inherent low phase noise,and exhibits a versatile range of applications in compact laser systems,promising advancements in portable instruments.
文摘In BEPC Ⅱ(Upgrade of Beijing Electron-Position Collider),multi-bunches and high current operation mode is usually used.Due to the influence of high frequency cavity structure or resistance impedance,the beam will be unstable.If the beam is unstable,the luminosity and brightness of the accelerator will be decreased.In order to improve the beam current and brightness of accelerator and the collider luminosity,the beam feedback system is needed to suppress the instability.The trifold frequency multiplier by using triode is simple to operate,and it has good performance.In the experiments,the 500MHz signal was passed through the Triode Frequency Multiplier to get the 1.5GHz signal,and its output amplitude stability is 1.7mV,and its synchronization stability is 3.46ps compared with the 500MHz input signal.
基金The National High Technology Research and Development Program of China (863 Program)(No.2007AA01Z2A7)the Scienceand Technology Program of Zhejiang Province (No.2008C16017)
文摘A fully integrated integer-N frequency synthesizer is implemented.The synthesizer is designed for low intermediate frequency (IF)ZigBee transceiver applications.Techniques used to make the loop bandwidth constant across the whole output frequency range of the voltage controlled oscillator(VCO)are adopted to maintain phase noise optimization and loop stability.In-phase and quadrature(IQ)signals are generated by a 1/2 frequency divider at the output of the VCO.The synthesizer is fabricated in 0.18 μm radio frequency(RF) complementary metal oxide semiconductor transistor (CMOS)technology.The chip area is 1.7 mm2.The synthesizer is measured on wafer.It consumes totally 28.8 mW excluding output buffers from a supply voltage of 1.8 V.The measured phase noise is -110 and -122 dBc/Hz at the offset of 1 and 3 MHz from a 2.405 GHz carrier,respectively.The measured reference spur at a 2 MHz offset from a 2.405 GHz carrier is-48.2 dBc.The measured setting time of the synthesizer is about 160 μs.
基金supported by the National Natural Science Foundation of China under Grant No. 61006027the New Century Excellent Talents Program of China under Grant No. NCET-10-0297
文摘The design procedure of an 1-GHz phase-locked loop (PLL)-based frequency synthesizer used in IEEE 1394b physical (PHY) system is presented in this paper. The PLL's loop dynamics are analyzed in depth and theoretical relationships between all loop parameters are clearly described. All the parameters are derived and verified by Verilog-A model, which ensures the accuracy and efficiency of the circuit design and simulation. A 4-stage ring oscillator is employed to generate 1-GHz oscillation frequency and is divided into low frequency clocks by a feedback divider. The architecture is a third-order, type-2 charge pump PLL. The simulated settling time is less than 4μs. The RMS value of period jitter of the PLL's output is 2.1 ps. The PLL core occupies an area of 0.12 mm2, one fourth of which is occupied by the MiM loop capacitors. The total current consumption of the chip is 16.5 mA. The chip has been sent for fabrication in 0.13 μm complementary metal oxide semiconductor (CMOS) technology.
基金Project supported by the National Natural Science Foundation of China(Grant No.11274115)the National Key Project for Basic Research,China(Grant No.2011CB808105)the National Key Scientific Instrument Project,China(Grant No.2012YQ150092)
文摘In this paper, we demonstrate a carrier envelope phase-stabilized Yb-doped fiber frequency comb seeding by a nonlinear-polarization-evolution(NPE) mode-locked laser at a repetition rate of 60 MHz with a pulse duration of 191 fs.The pump-induced carrier envelope offset frequency( f0) nonlinear tuning is discussed and further explained by the spectrum shift of the laser pulse. Through the environmental noise suppression, the drift of the free-running f0 is reduced down to less than 3 MHz within an hour. By feedback control on the pump power with a self-made phase-lock loop(PLL)electronics the carrier envelope offset frequency is well phase-locked with a frequency jitter of 85 m Hz within an hour.
基金Project supported by the Young Scientists Fund of the National Natural Science Foundation of China(Grant No.61401373)the Research Fund for the Doctoral Program of Southwest University,China(Grant No.SWU111030)
文摘A bandwidth microwave second harmonic generator is successfully designed using composite right/left-handed non- linear transmission lines (CRLH NLTLs) in a GaAs monolithic microwave integrated circuit (MMIC) technology. The structure parameters of CRLH NLTLs, e.g. host transmission line, rectangular spiral inductor, and nonlinear capacitor, have a great impact on the second harmonic performance enhancement in terms of second harmonic frequency, output power, and conversion efficiency. It has been experimentally demonstrated that the second harmonic frequency is deter- mined by the anomalous dispersion of CRLH NLTLs and can be significantly improved by effectively adjusting these structure parameters. A good agreement between the measured and simulated second harmonic performances of Ka-band CRLH NLTLs frequency multipliers is successfully achieved, which further validates the design approach of frequency multipliers on CRLH NLTLs and indicates the potentials of CRLH NLTLs in terms of the generation of microwave and millimeter-wave signal source.
基金Funded by the Communication System Project of Jiangsu Provincial Education Committee under grant No.JHB04010
文摘A fully integrated frequency synthesizer with low jitter and low power consumption in 0.18 μm CMOS (complementary metal-oxide semiconductor) technology is proposed in this paper.The frequency synthesizer uses a novel single-end gain-boosting charge pump, a differential coupled voltage controlled oscillator (VCO) and a dynamic logic phase/frequency detecor (PFD) to acquire low output jitter.The output frequency range of the frequency synthesizer is up to 1 200 MHz to 1 400 MHz for GPS (global position system) application.The post simulation results show that the phase noise of VCO is only 127.1 dBc/Hz at a 1 MHz offset and the Vp-p jitter of the frequency synthesizer output clock is 13.65 ps.The power consumption of the frequency synthesizer not including the divider is 4.8 mW for 1.8 V supply and it occupies a 0.8 mm×0.7 mm chip area.
基金This work was supported in part by Lodam A/S and in part by the PSO-ELFORSK Program。
文摘High quality speed information is one of the key issues in machine sensorless drives,which often requires proper filtering of the estimated speed.This paper comparatively studies typical low-pass filters(LPF)and phase-locked loop(PLL)type filters with respect to ramp speed reference tracking and steady-state performances,as well as the achievement of adaptive cutoff frequency control.An improved LPF-based filter structure with no ramping and steady-state errors caused by filter parameter quantization effects is proposed,which is suitable for applying LPF for sensorless drives of AC machines,especially when fixed-point digital signal processor is selected e.g.in mass production.Furthermore,the potential of adopting PLL for speed filtering is explored.It is demonstrated that PLL type filters can well maintain the advantages offered by the improved LPF.Moreover,it is found that the PLL type filters exhibit almost linear relationship between the cutoff frequency of the PLL filter and its proportional-integral(PI)gains,which can ease the realization of speed filters with adaptive cutoff frequency for improving the speed transient performance.The proposed filters are verified experimentally.The PLL type filter with adaptive cutoff frequency can provide satisfactory performances under various operating conditions and is therefore recommended.
文摘The phase-locking process is studied for high-power gyrotron oscillator driven by an external signal. The phase-locking nonlinear differential equations are derived, and the condition of phase-locking is shown and analyzed. The phase-locking signal can be introduced after gyrotron oscillates into saturation or before it. Two different ways of inputting signal make markable influence on the phase-locking process, this phenomenon is discussed. In this paper, the numerical calculations and analysis are given for gyrotron TE13 mode.
基金supported by the Science and Technology Project of the State Grid Corporation of China(SGRIZLKJ[2015]457)。
文摘A control strategy of frequency self-adaptation without phase-locked loop(PLL)underαβstationary reference frame(αβ-SRF)for a VSC-HVDC system is presented to improve the operational performance of the system under severe harmonic distortion conditions.The control strategy helps to eliminate the cross-coupling under dq synchronous reference frame(dq-SRF),and is achieved through two key technologies:1)positive phase sequence(PPS)and negative phase sequence(NPS)fundamental components are extracted from the AC grid voltage with an improved multiple complex coefficient filter(IMCF),and 2)grid instantaneous frequency is rapidly and precisely tracked using a frequency self-adaptation tracking algorithm(FATA)without PLL.The proposed strategy is applied to a point-to-point VSCHVDC system and validated by means of simulations.The results are compared to those with the traditional vector control strategy under dq-SRF.Simulation results illustrate that the proposed strategy results in better system performance than that with the traditional strategy in terms of harmonic suppression under normal and severe operating conditions of the AC system.
文摘Natural frequencies for multilayer plates are calculated by mixed finite element method. The main object of this paper is to use the mixed model for multilayer plates, analyzing each layer as an isolated plate, where the continuity of displacements is achieved by Lagrange multipliers (representing static variables). This procedure allows us to work with any model for single plate (so as to ensure the proper behavior of each layer), and the complexity of the multilayer system is avoided by ensuring the condition of displacements by the Lagrange multipliers (static variables). The plate is discretized by finite element modeling based on a primary hybrid model, where the domain is divided by quadrilateral, both for the displacement field and static variables. This mixed element for plates was implemented and several examples of vibrations have been verified successfully by the results obtained by other methods in the literature.
文摘From the point of view of system design, a configuration of fiber-optic interferomet- ric hydrophone array and its modulation and demodulation approach using frequncy division multiplexing technique based on Phase Generated Carrier (PGC) is introduced. And the em- phasis on demonstrating the relationship among the number of units N, the detectable signal amplitude D and the detectable frequency ws through analyzing the frequency spectrum of the output signal of the J × K array and the key factor which restricts N, D, Ws for increasing are presented. The maximum phare shift and the law of its variation according to frequency are specially analyzed. The results induced from some relative theory were verified by experiments.
文摘太赫兹源的输出功率是限制太赫兹技术远距离应用的重要参数。为了实现高效的太赫兹倍频器,基于高频特性下肖特基二极管的有源区电气模型建模方法,利用指标参数不同的两种肖特基二极管,研制出了两种170 GHz平衡式倍频器。所采用的肖特基二极管有源结区模型完善地考虑了二极管IV特性,载流子饱和速率限制,直流串联电阻以及趋肤效应等特性。通过对两种倍频器仿真结果进行对比,完备地分析了二极管主要指标参数对倍频器性能的影响。最后测试结果显示两种平衡式170 GHz倍频器在155~178 GHz工作带宽内的最高倍频效率分别大于11%和24%,最高输出功率分别大于15 m W和25 m W。从仿真和测试结果表示,采用的肖特基二极管建模方法和平衡式倍频器结构适用于研制高效的太赫兹倍频器。
基金The National Natural Science Foundation of China(No. 60974116 )the Research Fund of Aeronautics Science (No.20090869007)Specialized Research Fund for the Doctoral Program of Higher Education (No. 200902861063)
文摘In order to effectively control the working state of the gyroscope in drive mode, the drive characteristics of the micro electromechanical system (MEMS) gyroscope are analyzed in principle. A novel drive circuit for the MEMS gyroscope in digital closed-loop control is proposed, which utilizes a digital phase-locked loop (PLL) in frequency control and an automatic gain control (AGC) method in amplitude control. A digital processing circuit with a field programmable gate array (FPGA) is designed and the experiments are carried out. The results indicate that when the temperature changes, the drive frequency can automatically track the resonant frequency of gyroscope in drive mode and that of the oscillating amplitude holds at a set value. And at room temperature, the relative deviation of the drive frequency is 0.624 ×10^-6 and the oscillating amplitude is 8.0 ×10^-6, which are 0. 094% and 18. 39% of the analog control program, respectively. Therefore, the control solution of the digital PLL in frequency and the AGC in amplitude is feasible.