A 1-GHz Charge Pump PLL Frequency Synthesizer for IEEE 1394b PHY

The design procedure of an 1-GHz phase-locked loop （PLL）-based frequency synthesizer used in IEEE 1394b physical （PHY） system is presented in this paper. The PLL＇s loop dynamics are analyzed in depth and theoretical relationships between all loop parameters are clearly described. All the parameters are derived and verified by Verilog-A model, which ensures the accuracy and efficiency of the circuit design and simulation. A 4-stage ring oscillator is employed to generate 1-GHz oscillation frequency and is divided into low frequency clocks by a feedback divider. The architecture is a third-order, type-2 charge pump PLL. The simulated settling time is less than 4μs. The RMS value of period jitter of the PLL＇s output is 2.1 ps. The PLL core occupies an area of 0.12 mm2, one fourth of which is occupied by the MiM loop capacitors. The total current consumption of the chip is 16.5 mA. The chip has been sent for fabrication in 0.13 μm complementary metal oxide semiconductor （CMOS） technology.

Frequency Synthesizer of Short-Wave SFH/MFSK System

The technology of DDS-driven PLL is introduced and a new scheme of frequency synthesizer which is suitable for SW SFH/MFSK System is presented in this paper. Based on the special requirement of SW communication, a model of the scheme is given and the results show that the frequency synthesizer has small frequency insteval (≤0.1 Hz), short switch pierod (<200 ms) and high frequency stability as crystal oseillator.

DDFS spurious signals due to amplitude quantization in absence of phase-accumulator truncation

Spurious signals in direct digital frequency synthesizers （DDFSs） are partly caused by amplitude quantization and phase truncation, which affect their application to many wireless telecommunication systems. These signals are deterministic and periodic in the time domain, so they appear as line spectra in the frequency domain. Two types of spurious signals due to amplitude quantization are exactly formulated and compared in the time and frequency domains respectively. Then the frequency spectra and power levels of the spurious signals due to amplitude quantization in the absence of phase-accumulator truncation are emphatically analyzed, and the effects of the DDFS parameter variations on the spurious signals are thoroughly studied by computer simulation. And several important conclusions are derived which can provide theoretical support for parameter choice and spurious performance evaluation in the application of DDFSs.

A fractional-N frequency synthesizer for wireless sensor network nodes

This paper presents a fractional-N frequency synthesizer for wireless sensor network（WSN） nodes. The proposed frequency synthesizer adopts a phase locked loop（PLL） based structure, which employs an LC voltagecontrolled oscillator（VCO） with small VCO gain（KVCO） and frequency step（fstep） variations, a charge pump（CP）with current changing in proportion with the division ratio and a 20-bit △∑ modulator, etc. To realize constant KVCO and fstep, a novel capacitor sub-bands grouping method is proposed. The VCO sub-groups＇ sizes are arranged according to the maximal allowed KVCOvariation of the system. Besides, a current mode logic divide-by-2 circuit with inside-loop buffers ensures the synthesizer generates I/Q quadrature signals robustly. This synthesizer is implemented in a 0.13μm CMOS process. Measurement results show that the frequency synthesizer has a frequency span from 2.07 to 3.11 GHz and the typical phase noise is 86：34 dBc/Hz at 100 k Hz offset and 114：17 dBc/Hz at 1 MHz offset with a loop bandwidth of about 200 k Hz, which meet the WSN nodes＇ requirements.

A fractional-N frequency divider for multi-standard wireless transceiver fabricated in 0.18μm CMOS process

With the rapid evolution of wireless communication technology, integrating various communication modes in a mobile terminal has become the popular trend. Because of this, multi-standard wireless technology is one of the hot spots in current research. This paper presents a wideband fractional-N frequency divider of the multi-standard wireless transceiver for many applications. High-speed divider-by-2 with traditional source- coupled-logic is designed for very wide band usage. Phase switching technique and a chain of divider-by-2/3 are applied to the programmable frequency divider with 0.5 step. The phase noise of the whole frequency synthesizer will be decreased by the narrower step of programmable frequency divider. A-E modulator is achieved by an improved MASH 1-1-1 structure. This structure has excellent performance in many ways, such as noise, spur and input dynamic range. Fabricated in TSMC 0.18/tin CMOS process, the fractional-N frequency divider occupies a chip area of 1130 × 510μm^2 and it can correctly divide within the frequency range of 0.8-9 GHz. With 1.8 V supply voltage, its division ratio ranges from 62.5 to 254 and the total current consumption is 29 mA.

A fully-differential phase-locked loop frequency synthesizer for 60-GHz wireless communication

A 40-GHz phase-locked loop（PLL） frequency synthesizer for 60-GHz wireless communication applications is presented. The electrical characteristics of the passive components in the VCO and LO buffers are accurately extracted with an electromagnetic simulator HFSS. A differential tuning technique is utilized in the voltage controlled oscillator（VCO） to achieve higher common-mode noise rejection and better phase noise performance. The VCO and the divider chain are powered by a 1.0 V supply while the phase-frequency detector（PFD）and the charge pump（CP） are powered by a 2.5 V supply to improve the linearity. The measurement results show that the total frequency locking range of the frequency synthesizer is from 37 to 41 GHz, and the phase noise from a 40 GHz carrier is –97.2 dBc/Hz at 1 MHz offset. Implemented in 65 nm CMOS, the synthesizer consumes a DC power of 62 m W, including all the buffers.

A class-CVCO based Σ–Δ fraction-N frequency synthesizer with AFC for 802.11ah applications

A 1.4-2 GHz phase-locked loop （PLL） ∑-△ fraction-N frequency synthesizer with automatic fre- quency control （AFC） for 802.1 lah applications is presented. A class-C voltage control oscillator （VCO） ranging from 1.4 to 2 GHz is integrated on-chip to save power for the sub-GHz band. A novel AFC algorithm is introduced to maintain the VCO oscillation at the start-up and automatically search for the appropriate control word of the switched-capacitor array to extend the PLL tuning range. A 20-bit third-order ∑-△ modulator is utilized to reduce the fraction spurs while achieving a frequency resolution that is lower than 30 Hz. The measurement results show that the frequency synthesizer has achieved a phase noise of 〈 -120 dBc/Hz at 1 MHz offset and consumes 11.1 mW from a 1.7 V supply. Moreover, compared with the traditional class-A counterparts, the phase noise in class-C mode has been improved by 5 dB under the same power consumption.

Low noise frequency synthesizer with self-calibrated voltage controlled oscillator and accurate AFC algorithm

A low noise phase locked loop （PLL） frequency synthesizer implemented in 65 nm CMOS technology is introduced. A VCO noise reduction method suited for short channel design is proposed to minimize PLL output phase noise. A self-calibrated voltage controlled oscillator is proposed in cooperation with the automatic frequency calibration circuit, whose accurate binary search algorithm helps reduce the VCO tuning curve coverage, which reduces the VCO noise contribution at PLL output phase noise. A low noise, charge pump is also introduced to extend the tuning voltage range of the proposed VCO, which further reduces its phase noise contribution. The frequency synthesizer generates 9.75-11.5 GHz high frequency wide band local oscillator （LO） carriers. Tested 11.5 GHz LO bears a phase noise of-104 dBc/Hz at 1 MHz frequency offset. The total power dissipation of the proposed frequency synthesizer is 48 mW. The area of the proposed frequency synthesizer is 0.3 mm^2, including bias circuits and buffers.

A constant loop bandwidth fractional-N frequency synthesizer for GNSS receivers

A constant loop bandwidth fractionalN frequency synthesizer for portable civilian global navigation satellite system （GNSS） receivers implemented in a 130 nm 1P6M CMOS process is introduced. Via discrete work ing regions, the LCVCO obtains a wide tuning range with a simple structure and small VCO gain. Spur suppression technology is proposed to minimize the phase offset introduced by PFD and charge pumps. The optimized band width is maintained by an auto loop calibration module to adjust the charge pump current when the PLL output frequency changes or the temperature varies. Measurement results show that this synthesizer attains an inband phase noise lower than 93 dBc at a 10 kHz offset and a spur less than 70 dBc; the bandwidth varies by 4 3% for all the GNSS signals. The whole synthesizer consumes 4.5 mA current from a 1 V supply, and its area （without the LO tested buffer） is 0.5 mm2.

A low power wide-band CMOS PLL frequency synthesizer for portable hybrid GNSS receiver

The design consideration and implementation of a CMOS frequency synthesizer for the portable hybrid global navigation satellite system are presented. The large tuning range is achieved by tuning curve compensation using an improved VCO resonant tank, which reduces the power consumption and obtains better phase noise performance. The circuit is validated by simulations and fabricated in a standard 0.18 μm 1P6M CMOS process. Close-loop phase noise measured is lower than -95 dBc at 200 kHz offset while the measured ttming range is 21.5% from 1.47 to 1.83 GHz. The proposed synthesizer including source coupled logic prescaler consumes 6.2 mA current from 1.8 V supply. The whole silicon required is only 0.53 mm2.

A wideband frequency synthesizer for a receiver application at multiple frequencies

An integer-N frequency synthesizer for a receiver application at multiple frequencies was implemented in 0.18μm 1P6M CMOS technology. The synthesizer generates 2.57 GHz, 2.52 GHz, 2.4 GHz and 2.25 GHz local signals for the receiver. A wide-range voltage-controlled oscillator （VCO） based on a reconfigurable LC tank with a binaryweighted switched capacitor array and a switched inductor array is employed to cover the desired frequencies with a sufficient margin. The measured tuning range of the VCO is from 1.76 to 2.59 GHz. From the carriers of 2.57 GHz, 2.52 GHz, 2.4 GHz and 2.25 GHz, the measured phase noises are -122.13 dBc/Hz, -122.19 dBc/Hz, -121.8 dBc/Hz and -121.05 dBc/Hz, at 1 MHz offset, respectively. Their in-band phase noises are -80.09 dBc/Hz, -80.29 dBc/Hz, -83.05 dBc/Hz and -86.38 dBc/Hz, respectively. The frequency synthesizer including buffers consumes a total power of 70 mW from a 2 V power supply. The chip size is 1.5 × 1 mm2.

A low phase noise and low spur PLL frequency synthesizer for GNSS receivers

A low phase noise and low spur phase locked loop （PLL） frequency synthesizer for use in global navigation satellite system （GNSS） receivers is proposed. To get a low spur, the symmetrical structure of the phase frequency detector （PFD） produces four control signals, which can reach the charge pump （CP） simultaneously, and an improved CP is realized to minimize the charge sharing and the charge injection and make the current matched. Additionally, the delay is controllable owing to the programmable PFD, so the dead zone of the CP can be eliminated. The output frequency of the VCO can be adjusted continuously and precisely by using a programmable LC-TANK. The phase noise of the VCO is lowered by using appropriate MOS sizes. The proposed PLL frequency synthesizer is fabricated in a 0.18 μm mixed-signal CMOS process. The measured phase noise at 1 MHz offset from the center frequency is -127.65 dBc/Hz and the reference spur is -73.58 dBc.

A fully integrated frequency synthesizer for a dual-mode GPS and Compass receiver

This paper presents a fully integrated frequency synthesizer for a dual-mode GPS and Compass receiver fabricated in a 0.13μm CMOS technology.The frequency synthesizer is implemented with an on-chip symmetric inductor and an on-chip loop filter.A capacitance multiplying approach is proposed in the on-chip loop filter design for area-saving consideration.Pulse-swallow topology with a multistage noise shaping△Σmodulator is adopted in the frequency divider design.The synthesizer generates local oscillating signals at 1571.328 MHz and 1568.259 MHz with a 16.368 MHz reference clock by working in integer and fractional modes.Measurement results show that the phase noise of the synthesizer achieves -91.3 dBc/Hz and -117 dBc/Hz out of band at 100 kHz and 1 MHz frequency offset,separately.The proposed frequency synthesizer consumes 8.6 mA from a 1.2 V power supply and occupies an area of 0.92 mm;.

A 0.20–2.43 GHz fractional-N frequency synthesizer with optimized VCO and reduced current mismatch CP

A 0.20–2.43 GHz fractional-N frequency synthesizer is presented for multi-band wireless communication systems,in which the scheme adopts low phase noise voltage-controlled oscillators(VCOs)and a charge pump(CP)with reduced current mismatch.VCOs that determine the out-band phase noise of a phase-locked loop(PLL)based frequency synthesizer are optimized using an automatic amplitude control technique and a high-quality factor figure-8-shaped inductor.A CP with a mismatch suppression architecture is proposed to improve the current match of the CP and reduce the PLL phase errors.Theoretical analysis is presented to investigate the influence of the current mismatch on the output performance of PLLs.Fabricated in a TSMC 0.18-μm CMOS process,the prototype operates from 0.20 to 2.43 GHz.The PLL synthesizer achieves an in-band phase noise of-96.8 dBc/Hz and an out-band phase noise of-122.8 dBc/Hz at the 2.43-GHz carrier.The root-mean-square jitter is 1.2 ps under the worst case,and the measured reference spurs are less than-65.3 dBc.The current consumption is 15.2 mA and the die occupies 850μm×920μm.

A Δ ∑ fractional-N frequency synthesizer for FM tuner using low noise filter and quantization noise suppression technique

A △∑ fractional-N frequency synthesizer fabricated in a 130 nm CMOS technology is presented for the application of an FM tuner. A low noise filter, occupying a small die area and decreasing the output noise, is integrated on a chip. A quantization noise suppression technique, using a reduced step size of the frequency divider, is also adopted. The proposed synthesizer needs no off-chip components and occupies an area of 0.7 mm2. The in-band phase noise （from 10 to 100 kHz） below -108 dBc/Hz and out-of-band phase noise of -122.9 dBc/Hz （at 1 MHz offset） are measured with a loop bandwidth of 200 kHz. The quantization noise suppression technique reduces the in-band and out-of band phase noise by 15 dB and 7 dB respectively. The integrated RMS phase error is no more than 0.48°. The proposed synthesizer consumes a total power of 7.4 mW and the frequency resolution is less than 1 Hz.

A fast lock frequency synthesizer using an improved adaptive frequency calibration

An improved adaptive frequency calibration（AFC） has been employed to implement a fast lock phaselocked loop based frequency synthesizer in a 0.18μm CMOS process.The AFC can work in two modes：the frequency calibration mode and the store/load mode.In the frequency calibration mode,a novel frequency-detector is used to reduce the frequency calibration time to 16 us typically.In the store/load mode,the AFC makes the voltage-controlled oscillator（VCO） return to the calibrated frequency in about 1μs by loading the calibration result stored after the frequency calibration.The experimental results show that the VCO tuning frequency range is about 620-920 MHz and the in-band phase noise within the loop bandwidth of 10 kHz is-82 dBc/Hz.The lock time is about 20μs in frequency calibration mode and about 5 us in store/load mode.The synthesizer consumes 12 mA from a single 1.8 V supply voltage when steady.

A 5 GHz CMOS frequency synthesizer with novel phase-switching prescaler and high-Q LC-VCO

A phase-locked loop（PLL） frequency synthesizer with a novel phase-switching prescaler and a high-Q LC voltage controlled oscillator（VCO） is presented.The phase-switching prescaler with a novel modulus control mechanism is much more robust on process variations.The Q factor of the inductor,I-MOS capacitors and varactors in the VCO are optimized.The proposed frequency synthesizer was fabricated by SMIC 0.13μm 1P8M MMRF CMOS technology with a chip area of 1150×2500μm^2.When locking at 5 GHz,the current consumption is 15 mA from a supply voltage of 1.2 V and the measured phase noise at a 1 MHz offset is -122.45 dBc/Hz.

A wide locking range and low DC power injection-locked frequency tripler for K-band application

This paper presents a wide locking range and low DC power injection-locked frequency tripler for Kband frequency synthesizers application. The proposed ILFT employs a variable current source to decouple the injection signal path and the bias current so that the third harmonic of the injection signal can be maximized to enlarge the locking range. Meanwhile, a 2-bit digital control capacity array is used to further increase the output frequency locking range. It is implemented in a 130-nm CMOS process and occupies a chip area of 0.7 ×0.8 mm^2 without pads. The measured results show that the proposed ILFT can achieve a whole locking range from 18 to21 GHz under the input signal of 4 dBm and the core circuit dissipates only 4 m W of DC power from a 0.8 V supply voltage. The measured phase noise degradation from that of the injection signal is only 10 dB at 1 MHz offset.

A low-power CMOS frequency synthesizer for GPS receivers

A low-power frequency synthesizer for GPS/Galileo L1/E1 band receivers implemented in a 0.18μm CMOS process is introduced.By adding clock-controlled transistors at latch outputs to reduce the time constant at sensing time,the working frequency of the high-speed source-coupled logic prescaler supplying quadrature local oscillator signals has been increased,compared with traditional prescalers.Measurement results show that this synthesizer achieves an in-band phase noise of-87 dBc/Hz at 15 kHz offset,with spurs less than-65 dBc.The whole synthesizer consumes 6 mA in the case of a 1.8 V supply,and its core area is 0.6 mm;.

A wideband frequency synthesizer with VCO and AFC co-design for fast calibration

A wideband fractional-N frequency synthesizer is implemented in a 65 nm CMOS process.It employs a wideband LC voltage-controlled oscillator（VCO） with optimized VCO gain（KVCO/and a sub-band step to improve automatic frequency calibration（AFC） efficiency at negligible expense of phase noise performance.An agile AFC is realized by direct mapping based on the division ratio,and optional redundant counting and comparing calibration is introduced accommodating PVT variations,which samples the reference clock using the prescaled VCO output as a discriminating clock.A charge pump with switched charging current is adopted to compensate for the loop bandwidth variation.Measurement results show this directly-mapped AFC locates the target sub-band in 100 ns and only needs 1.2 s for redundant calibration.The frequency synthesizer spans a frequency range from 0.62 to 1.52 GHz,with phase noise of-86 dBc/Hz at 10 kHz offset and-122 dBc/Hz at 1 MHz offset while consuming 9.76 mA from a 1.2 V supply.