A super-high resolution frequency standard measuring approach based on phase coincidence characteristics between signals

A method for super high resolution comparison measurement is proposed in this paper with a comparison between the frequency standards of different nominal frequencies, which is based on phase coincidence detection of the two compared signals. It utilizes the regular phase shift characteristics between the signals. The resolution of the measurement approach can reach 10^-13/s at 5 MHz, and the self-calibration resolution can achieve 10^-14/s in the comparison between 10 MHz and 100 MHz, or even can reach 10^-15/s in the comparison between 10 MHz and 190 MHz. This method implies significant progress in the development of the high precision frequency standard comparison technology.

Direct Digital Frequency Control Based on the Phase Step Change Characteristic between Signals

We present a new digital phase lock technology to achieve the frequency control and transformation through high precision multi-cycle group synchronization between signals without the frequency transformation circuit. In the case of digital sampling, the passing zero point of the phase of the controlled signal has the phase step characteristic, the phase step of the passing zero point is monotonic continuous with high resolution in the phase lock process, and using the border effect of digital fuzzy area, the gate can synchronize with the two signals, the quantization error is reduced. This technique is quite different from the existing methods of frequency transformation and frequency synthesis, the phase change characteristic between the periodic signals with different nominal is used. The phase change has the periodic phenomenon, and it has the high resolution step value. With the application of the physical law, the noise is reduced because of simplifying frequency transformation circuits, and the phase is locked with high precision. The regular phase change between frequency signals is only used for frequency measurement, and the change has evident randomness, but this randomness is greatly reduced in frequency control, and the certainty of the process result is clear. The experiment shows that the short term frequency stability can reach 10-12/s orders of magnitude.

High resolution range profile analysis based on multicarrier phase-coded waveforms of OFDM radar

Orthogonal frequency division multiplexing（OFDM） radar with multicarrier phase-coded waveforms has been recently introduced to achieve high range resolution.The conventional method for obtaining the high resolution range profile（HRRP） is based on matched filters.A method of synthesizing HRRP based on the fast Fourier transform（FFT） and decoding is proposed.The mathematical expressions of HRRP are derived by assuming an elementary scenario of point-scattering targets.Based on the characteristic of OFDM multicarrier signals,it mainly analyzes the influence on HRRP exerted by several factors,such as velocity compensation errors,the sampling frequency offset,and so on.The conclusions are significant for the design of the OFDM imaging radar.Finally,the simulation results demonstrate the validity of the conclusions.

Kautz Function Based Continuous-Time Model Predictive Controller for Load Frequency Control in a Multi-Area Power System

A continuous-time Model Predictive Controller was proposed using Kautz function in order to improve the performance of Load Frequency Control(LFC).A dynamic model of an interconnected power system was used for Model Predictive Controller(MPC)design.MPC predicts the future trajectory of the dynamic model by calculating the optimal closed loop feedback gain matrix.In this paper,the optimal closed loop feedback gain matrix was calculated using Kautz function.Being an Orthonormal Basis Function(OBF),Kautz function has an advantage of solving complex pole-based nonlinear system.Genetic Algorithm(GA)was applied to optimally tune the Kautz function-based MPC.A constraint based on phase plane analysis was implemented with the cost function in order to improve the robustness of the Kautz function-based MPC.The proposed method was simulated with three area interconnected power system and the efficiency of the proposed method was measured and exhibited by comparing with conventional Proportional and Integral(PI)controller and Linear Quadratic Regulation(LQR).

A 5-GHz frequency synthesizer with constant bandwidth for low IF ZigBee transceiver applications

A fully integrated integer-N frequency synthesizer is implemented.The synthesizer is designed for low intermediate frequency （IF）ZigBee transceiver applications.Techniques used to make the loop bandwidth constant across the whole output frequency range of the voltage controlled oscillator（VCO）are adopted to maintain phase noise optimization and loop stability.In-phase and quadrature（IQ）signals are generated by a 1/2 frequency divider at the output of the VCO.The synthesizer is fabricated in 0.18 μm radio frequency（RF） complementary metal oxide semiconductor transistor （CMOS）technology.The chip area is 1.7 mm2.The synthesizer is measured on wafer.It consumes totally 28.8 mW excluding output buffers from a supply voltage of 1.8 V.The measured phase noise is -110 and -122 dBc/Hz at the offset of 1 and 3 MHz from a 2.405 GHz carrier,respectively.The measured reference spur at a 2 MHz offset from a 2.405 GHz carrier is-48.2 dBc.The measured setting time of the synthesizer is about 160 μs.

2.7-4.0 GHz PLL with dual-mode auto frequency calibration for navigation system on chip

A 2.7-4.0 GHz dual-mode auto frequency calibration(AFC) fast locking PLL was designed for navigation system on chip(SoC). The SoC was composed of one radio frequency(RF) receiver, one baseband and several system control parts. In the proposed AFC block, both analog and digital modes were designed to complete the AFC process. In analog mode, the analog part sampled and detected the charge pump output tuning voltage, which would give the indicator to digital part to adjust the voltage control oscillator(VCO) capacitor bank. In digital mode, the digital part counted the phase lock loop(PLL) divided clock to judge whether VCO frequency was fast or slow. The analog and digital modes completed the auto frequency calibration function independently by internal switch. By designing a special switching algorithm, the switch of the digital and analog mode could be realized anytime during the lock and unlock detecting process for faster and more stable locking. This chip is fabricated in 0.13 μm RF complementary metal oxide semiconductor(CMOS) process, and the VCO supports the frequency range from 2.7 to 4.0 GHz. Tested 3.96 GHz frequency phase noise is -90 d Bc/Hz@100 k Hz frequency offset and -120 d Bc/Hz@1 MHz frequency offset. By using the analog mode in lock detection and digital mode in unlock detection, tested AFC time is less than 9 μs and the total PLL lock time is less than 19 μs. The SoC acquisition and tracking sensitivity are about-142 d Bm and-155 d Bm, respectively. The area of the proposed PLL is 0.35 mm^2 and the total SoC area is about 9.6 mm^2.

A 1.2-to-1.4 GHz low-jitter frequency synthesizer for GPS application

A fully integrated frequency synthesizer with low jitter and low power consumption in 0.18 μm CMOS (complementary metal-oxide semiconductor) technology is proposed in this paper.The frequency synthesizer uses a novel single-end gain-boosting charge pump, a differential coupled voltage controlled oscillator (VCO) and a dynamic logic phase/frequency detecor (PFD) to acquire low output jitter.The output frequency range of the frequency synthesizer is up to 1 200 MHz to 1 400 MHz for GPS (global position system) application.The post simulation results show that the phase noise of VCO is only 127.1 dBc/Hz at a 1 MHz offset and the Vp-p jitter of the frequency synthesizer output clock is 13.65 ps.The power consumption of the frequency synthesizer not including the divider is 4.8 mW for 1.8 V supply and it occupies a 0.8 mm×0.7 mm chip area.

Low Phase Noise VCO using Novel Harmonic Control Circuit Based on Quad-band Composite Right/Left-handed Transmission Line

In this paper, a novel Voltage-Controlled Oscillator （VCO） using the harmonic control circuit based on the quad-band Composite Right/Left-Handed （CRLH） Transmission Line （TL） is presented to reduce the phase noise without the reduction of the frequeacy tuning range and miniaturizing the circuit size. The phase noise has been reduced by the quad-band harmonic control circuit which has the short impedance for the second- and third- and fourth- and fifth-hannonic components. The CRLH TL with two Left-Handed （LH） （backward） and two Right-Handed （RH） （forward） pass bands are used to design the quad-band harmonic control circuit. The high- Q resonator has been used to reduce the phase noise, but it has the problem of the frequency timing range reduction. However, the frequency tuning range of the proposed VCO has not reduced because the phase noise has reduced without the high-Q resonator. The miniaturization of the circuit size is achieved by using the quad-band CRLH TL instead of the conventional RH TL, The phase noise of VCO is - 124.43～ - 122.67 dBc/Hz at 100 kHz in the tuning range of 5. 729 ～5.934 GHz.

Research on a New Control Strategy of Three Phase Inverter for Unbalanced Loads

One of the very important functions of three-phase inverter is to maintain the symmetric three-phase output voltage when the three-phase loads are unbalanced. Although the traditional symmetrical component decomposing and superimpose theory can keep the voltage balance through compensating the positive-, negative- and zero-sequence components of the output voltage of inverter, however, this method is time-consuming and not suitable for control. Aiming at high power medium frequency inverter source, a P+Resonant (Proportion and Resonant) controller which ensured a balanced three phase output voltage under unbalanced load is proposed in this paper. The regulator was proved to be applicable to both three-phase three-wire system and three-phase four-wire system and developed two methods of realization. The simulation results verified that this method can suppressed effectively the output voltage distorted caused by the unbalanced load and attained a high quality voltage waveforms.

基于对称控制的三相并网变流器单输入单输出阻抗建模与分析

三相并网变流器的不对称控制结构会导致频率耦合效应,降低其接入弱电网的稳定裕度,增加了阻抗分析的复杂度。首先,该文提出一种三相并网变流器的对称控制策略,以消除由锁相环和直流电压环引起的频率耦合效应。该控制策略通过在控制环路中引入直流电压环q轴补偿,以形成对称的直流电压闭环结构,同时引入对称锁相环,消除传统锁相环的非对称动态特性。因此,三相并网变流器可建模为单输入单输出的阻抗复矢量形式,进而可采用标准奈奎斯特准则进行阻抗稳定性分析,能够直观地说明控制器对系统阻抗特性的主导作用。然后,对并网变流器的阻抗特性进行分析,得出弱电网中对称锁相环的带宽对系统稳定性有着至关重要的影响,并且,不同运行工况也会改变并网变流器的阻抗特性,进而影响系统的稳定性。最后,仿真和实验结果验证了所提控制策略对频率耦合效应抑制的有效性以及阻抗特性分析的准确性。

基于基准频率自适应谐波准谐振控制器的宽变频逆变电源控制研究

360~800 Hz宽变频交流电源系统是多电飞机电力系统的主要发展方向之一。为实现宽变频中频逆变电源在包括带整流型非线性负载等工况下的宽范围谐波抑制,保证其任意基准频率下的输出电压质量,提出一种基于频率基准自适应谐波准谐振控制器的控制策略。基于滤波电感电流反馈,设计了包含数字控制延迟补偿的有源阻尼方案,以抑制输出滤波器的谐振尖峰,对电压控制器的被控对象进行校正使系统得到简化;设计并采用积分与准比例谐振相结合的基波追踪控制器以消除基波频段的稳态误差;提出基准频率自适应的补偿角度设计方法以实现谐波准谐振控制在电压环控制带宽之外的谐波抑制。在理论分析的基础上,搭建了一台300~800 Hz/600 W单相逆变器样机并进行实验测试,结果表明,采用该控制策略的逆变器能够实现宽基波频段内任意基准频率下的宽范围谐波抑制,且具有良好的稳态和动态输出特性。

电网次同步振荡对光伏发电系统的影响分析及抑制策略研究

在电网发生次同步振荡(sub-synchronous oscillation,SSO)时,光伏(photovoltaic,PV)并网逆变器的工作性能会受到干扰,影响PV发电系统的稳定性。针对这一问题,文中首先分析锁相环(phase-locked loop,PLL)输出相位扰动对于坐标变换过程的影响,建立计及相位扰动的PV并网逆变器的数学模型,梳理电网SSO对PV并网逆变器产生扰动的机理,并将扰动分为物理扰动量以及误差扰动量;其次,设计改进型PLL以消除相位引起的误差扰动量对PV发电系统的影响;再次,针对不同目标下的抑制效果进行对比分析,同时确定振荡电压特性对控制器产生影响的关键因素。依据上述研究,提出一种基于自适应准谐振控制器的PV发电系统功率振荡抑制策略。最后,通过搭建实验平台,对所提控制策略的有效性进行验证。

晶闸管和IGBT混合的三相电机两相变频控制策略

现有三相交直交变频电路中大多使用IGBT作为电力电子器件,为了进一步降低低压大容量变频器设备成本,减少IGBT的使用,提出了一种晶闸管和IGBT混合的三相电机两相变频电路结构及四开关八电压矢量直接转矩控制策略.首先分析了利用IGBT辅助晶闸管关断的三相电机两相变频电路结构,并分析了不同开关状态下的瞬时电路工作原理,给出三相四开关拓扑下的八电压矢量生成方法;其次提出四开关八矢量异步电机直接转矩控制策略,并给出扇区划分、电压矢量选择和电压矢量伏秒生成原理;最后通过仿真实验验证所提策略的正确性和可行性.仿真结果验证了上述电路结构和控制方法的有效性.

基于地震频相融合的智能化高分辨率反演

目前的地震反演主要以模型驱动为主,对噪声较敏感,反演结果的分辨率往往较低,通常只使用地震数据的振幅信息,没有充分利用相位信息。研究表明,波阻抗和地震振幅、相位的相关性较强,因此联合应用振幅谱和相位谱可以有效减小反演结果的多解性。为此,结合深度学习与地震数据的频(振幅谱)、相(相位谱)信息,提出基于数据驱动的频相智能波阻抗反演,有效提高了反演结果的分辨率和精度。具体步骤为:(1)基于高分辨率时频分析提取地震道的频相信息;(2)应用图像处理技术融合频相信息;(3)结合频相信息和地层波阻抗制作数据标签对,用数据标签对训练优选的深度网络;(4)提取待反演三维地震数据的频相信息并输入训练好的深度网络,即可得到高分辨率波阻抗反演结果。与现有的深度学习地震反演方法相比,所提方法主要创新点在于首次在地震反演中同时应用了地震数据的频相信息。模型测试结果表明,频相信息的联合应用有效地减小了反演结果的多解性,提高了反演精度。实际应用结果表明,与传统的稀疏脉冲反演相比,所提方法提高了反演结果的纵向分辨率,益于进一步推广、应用。

电网故障下含直驱风电机组的电力系统频率动态响应分析

电网受扰后基于模型解析的频率响应分析对电力系统安全评估与紧急控制具有重要意义。电网发生故障时,直驱风电机组(DDWT)并网点电压幅值跌落引发控制器暂态响应,同时电压相位突变引发锁相暂态响应,锁相暂态响应又通过变流器控制传导产生功率控制误差,可能导致现有以负荷突变场景为对象的频率特性分析产生较大偏差。为此,提出了电网故障下DDWT锁相偏差的量化方法;解析了锁相偏差经DDWT变流器控制的传导路径,提出了锁相暂态响应导致DDWT功率控制误差的机理及其计算方法;建立了电网故障下含DDWT的电力系统频率响应模型,提出了锁相暂态响应影响下系统频率变化率和最大频率偏差的计算方法,解析了电网故障下考虑DDWT功率控制误差的电力系统频率动态响应特性,并通过算例分析验证了所提方法的有效性。

基于SSO多扰动输入机理分析的DFIG-GSC功率振荡抑制策略研究

电网次同步振荡(SSO)已成为桎梏新能源发展的主要问题之一,针对SSO下双馈感应发电机(DFIG)中网侧变流器(GSC)的功率振荡问题展开研究。首先,建立SSO对GSC的多扰动输入数学模型,探究不同扰动输入的性质以及其对GSC系统的影响,明确了针对物理量扰动以及信号扰动分别采用补偿与滤除两种不同的抑制方法。其次,针对锁相环(PLL)输出误差经过坐标变换产生耦合振荡的问题,建立PLL输出误差角度的频域数学模型,并通过设计一种改进PLL消除其输出误差对GSC的信号扰动影响。同时,设计一种准谐振控制器的自适应算法,并提出基于自适应准谐振控制器的DFIG-GSC功率振荡抑制策略,消除SSO对GSC的物理扰动影响;最后,通过搭建具有SSO模拟环境的DFIG实验平台,验证本文所提控制策略的有效性。

CLLLC谐振变换器的分级寻优模型预测控制

针对CLLLC谐振变换器提出了一种基于分级寻优模型预测的混合控制策略。通过结合变频控制与移相控制的优点,在实现软开关的同时,能拓宽变换器的电压增益范围。该策略不仅减小了普通有限集模型预测控制(MPC)策略的计算量,还改善了PI控制存在的电压超调大和动态响应慢的问题,在稳态性能相近的情况下提升了变换器系统的动态性能。最后通过Matlab/Simulink仿真和实验证明了分级寻优MPC策略的有效性。

定频移相控制六开关双谐振变换器研究

针对传统频率控制的LLC谐振变换器在宽电压应用中电压调节性能差且循环电流较大的问题,设计一种六开关双谐振LLC变换器。该变换器由2个全桥LLC谐振变换器共用1个桥臂混合组成。相较于传统的频率控制,该变换器采用定频移相控制调节输出电压,减小开关频率范围。根据2个变压器连接方式的不同,变换器有2种拓扑形态。当2个变压器顺极性串联时,变换器的增益范围为0~1,可以实现超宽输出电压;当2个变压器反极性串联时,变换器的增益范围为1~2,在工作过程中具有较小的环流损耗。2种拓扑形态下,原边开关管和副边二极管分别实现ZVS开通和ZCS关断。最后,通过Simulink仿真和实验验证了研究内容的有效性。

双三相永磁同步电机改进型模型预测电流控制

针对双三相永磁同步电机模型预测共模电压抑制方法存在寻优计算量大、开关频率较高、稳态性能不佳的问题,提出一种改进型模型预测电流控制.首先,改进六相两电平逆变器,降低零矢量共模电压幅值;其次,选择小共模电压矢量构造虚拟电压矢量,简化价值函数的同时减小共模电压和电流谐波含量;再次,通过计算参考电压矢量直接选择最优电压矢量以减少寻优次数,并引入占空比控制提升电机控制精度,改善电机稳态性能.最后,仿真对比传统模型预测电流控制、RCMV(Reduced Common Mode Voltage)-1、RCMV-2和所提控制方法.结果表明,所提控制方法在减小共模电压的同时,降低了转矩脉动和谐波电流,且较RCMV-2方法开关频率明显降低;此外,寻优代码执行时间相较于RCMV-1和RCMV-2分别降低了约91%和65%,减小了计算量.

低抖动电荷泵锁相环设计及其Simulink建模仿真

随着集成电路工艺技术的进步,电路工作频率越来越高,对时钟信号的抖动和相噪也提出了更高的要求。针对锁相环电路参数多、结构复杂、瞬态仿真耗时长等问题,通过建立电荷泵锁相环系统环路数学模型,并运用MATLAB/Simulink对其进行负反馈系统建模,实现对电荷泵锁相环的快速动态仿真。在TSMC 65 nm CMOS工艺节点下,完成了锁相环的电路设计、版图绘制、物理验证并提取寄生参数及后仿真,得到一款典型值:输入频率为30 MHz,锁定频率1.5 GHz的低抖动电荷泵锁相环。后仿真结果表明该PLL电路性能指标良好,在典型值条件下,PLL的锁定时间为10μs,锁定时峰峰值抖动为2.68 ps,时钟信号占空比为45%。