Design of a Low-Noise Front-End Readout Circuit for CdZnTe Detectors

In this paper, the design of a novel low-noise front-end readout circuit for Cadmium zinc telluride (CdZnTe) X-ray and γ-ray detectors is described. The front-end readout circuits include the charge sensitive amplifier (CSA) and the CR-RC shaper is implemented in TSMC 0.35 μm mixed-signal CMOS technology. The die size of the prototype chip is 4.9 mm × 2.2 mm. The simulation results show that, the noise performance is 46 electrons + 10 electrons/pF, and power consumption is 1.65 mW per channel.

A Fully Integrated CMOS Readout Circuit for Particle Detectors

Novel schemes for a charge sensitive amplifier （CSA） and a CR-（RC）, semi-Gaussian shaper in a fully integrated CMOS readout circuit for particle detectors are presented. The CSA is designed with poly-resistors as feedback components to reduce noise. Compared with conventional CSA, the input referred equivalent noise charge（ENC） is simulated to be reduced from 5036e to 2381e with a large detector capacitance of 150pF at the cost of 0.5V output swing loss. The CR-（RC）,semi-Gaussian shaper uses MOS transistors in the triode region in series with poly-resistors to compensate process variation without much linearity reduction.

Design and implementation of GM- APD array readout circuit for infrared imaging

Based on an avalanche photodiode（ APD） detecting array working in Geiger mode（ GM-APD）, a high-performance infrared sensor readout integrated circuit（ ROIC） used for infrared 3D（ three-dimensional） imaging is proposed. The system mainly consists of three functional modules, including active quenching circuit（ AQC）, time-to-digital converter（ TDC） circuit and other timing controller circuit. Each AQC and TDC circuit together constitutes the pixel circuit. Under the cooperation with other modules, the current signal generated by the GM-APD sensor is detected by the AQC, and the photon time-of-flight（ TOF） is measured and converted to a digital signal output to achieve a better noise suppression and a higher detection sensitivity by the TDC. The ROIC circuit is fabricated by the CSMC 0. 5 μm standard CMOS technology. The array size is 8 × 8, and the center distance of two adjacent cells is 100μm. The measurement results of the chip showthat the performance of the circuit is good, and the chip can achieve 1 ns time resolution with a 250 MHz reference clock, and the circuit can be used in the array structure of the infrared detection system or focal plane array（ FPA）.

Design of Diode Type Un-Cooled Infrared Focal Plane Array Readout Circuit

The diode infrared focal plane array uses the silicon diodes as a sensitive device for infrared signal measurement. By the infrared radiation, the infrared focal plane can produces small voltage signals. For the traditional readout circuit structures are designed to process current signals, they cannot be applied to it. In this paper, a new readout circuit for the diode un-cooled infrared focal plane array is developed. The principle of detector array signal readout and small signal amplification is given in detail. The readout circuit is designed and simulated by using the Central Semiconductor Manufacturing Corporation （CSMC） 0.5 μm complementary metal-oxide-semiconductor transistor （CMOS） technology library. Cadence Spectre simulation results show that the scheme can be applied to the CMOS readout integrated circuit （ROIC） with a larger array, such as 320×240 size array.

Particle detector readout integrated circuit of 0.18μm technology with 164 e equivalent noise charge

Integrated circuits of deep submicron(DSM) CMOS technology are advantageous in volume density, power consumption and thermal noise for multichannel particle detection systems,but there are challenges in the front-end circuit design.In this paper,we present a 0.18μm CMOS front-end readout circuit for low noise CdZnTe detectors in tens of pF capacitance.Solutions to the noise and gate leak problems in DSM technologies are discussed in detail.A prototype chip was designed,with a charge sensitive preamplifier,a 4th order semi-Gaussian shaper and several output drivers.Test results show that the chip has an equivalent noise charge of 164 e,without connecting it to a detector,with an integral nonlinearity of<0.21%and differential nonlinearity of<3.75%.

Design and test results of a low-noise readout integrated circuit for high-energy particle detectors

A low-noise readout integrated circuit for high-energy particle detector is presented.The noise of charge sensitive amplifier was suppressed by using single-side amplifier and resistors as source degeneration.Continuous-time semi-Gaussian filter is chosen to avoid switch noise.The peaking time of pulse shaper and the gain can be programmed to satisfy multi-application.The readout integrated circuit has been designed and fabricated using a 0.35 μm double-poly triple-metal CMOS technology.Test results show the functions of the readout integrated circuit are correct.The equivalent noise charge with no detector connected is 500–700 e in the typical mode,the gain is tunable within 13–130 mV/fC and the peaking time varies from 0.7 to 1.6 μs,in which the average gain is about 20.5 mV/fC,and the linearity reaches 99.2%.

Design of a Low-Noise Front-End Readout CSP-Shaper System for CZT Detectors

This paper describes a low-noise front-end readout circuit for CZT detectors based on TSMC 0.35 um mixed-single CMOS technology;mainly analyzes the noise model of the detector-preamplifier and presents the low-noise circuit schematic of charge sensitive preamplifier and shaper. Considering the parasitical influences, the circuit and layout-design are optimized to reduce noise. The preliminary simulation results show that, the equivalent noise charge (ENC) is 74 e﹣ (rms), noise slope is 9 e﹣/pF, power consumption is 2 mW, and non-linearity

Study of Reducing Non-Ideal Effects Based on TiN Sensitive Electrode with Front-End Offset Circuit

The structure of the extended gate ion sensitive field effect transistor (EGISFET) is similar to the structure of the ion sensitive field effect transistor (ISFET).Moreover,the non-ideal effect of EGISFET is the main impediment to development of commercial processes for sensitive devices.It is necessary to promote the stability and reliability of the devices by employing calibration circuits and the better fabrication conditions.The temporal drift exists in the entire measurement experiment. Furthermore,in this study we can reduce the temporal drift effect which influences the stability of the TiN sensitive electrode with the differential front-end offset circuit.The measurement system combines with shifting circuit,differential and instrument amplifiers.We employ the calibration circuit to compare with the variations of the output voltage,and expectably improve the stability and reliability of the TiN sensitive electrode by the novel calibration circuit.

Low Noise Readout Circuit for Biosensor SoC

Presented is a low noise interface circuit that is tuned to the needs of self-assembly monolayers biosensor SoC. The correlated double sampling(CDS) unit of the readout circuit can reduce 1/f noise, KTC noise and fixed noise of micro arrays effectively. The circuit is simulated in a 0.6 μm/level 7 standard CMOS process, and the simulated results show the output voltage has a good linearity with the transducing current of the micro arrays. This is a novel circuit including four amplifiers sharing a common half-circuit and the noise reducing CDS unit. It could be widely used for micro array biosensors.

Readout circuit with nonuniformity correction for the uncooled microbolometer

The output of uncooled microbolometer is nonuniform, and the traditional two-point nonuniformity correction method requires a tight restriction on substrate temperature. The circuit proposed by this article can relax the restriction on the substrate temperature and perform nonuniformity correction when reading out the image signal. The dummy pixels reduce static current. And the Column shared DACs transfer correction data to the gates of MOS transistors and the positive reference edge of amplifier, to control the bias current of detector and dummy one, and set the start point of integration. This circuit has higher sensitivity, wider dynamic range, and frame frequency of more than 30 Hz for 128×128 array. PSPICE simulation results seem that this circuit functions well.

Design of a Novel Front-End Readout ASIC for PET Imaging System

The architecture of a multi-channel front-end system is important for realizing a high-resolution PET system. We propose a novel front-end readout electronic system with TDC to deal with time information for PET system which can easily design the timing control. Each channel consists of a charge preamplifier, slow/fast shaper, discriminator and an analog memory. There are an ADC and a TDC to process the energy information and time information for each channel at the same time. In this paper, the whole system signals flow is all simulated by MATLAB. The simulation results show that the proposed system can process slender current from the detector and achieve the energy and time information. The proposed architecture can be applied to high-resolution PET imaging systems with multi-channel ASICs.

Design of a high-dynamic-range prototype readout system for VLAST calorimeter

In the future, the Very Large Area gamma-ray Space Telescope is expected to observe high-energy electrons and gamma rays in the MeV to TeV range with unprecedented acceptance. As part of the detector suite, a high-energy imaging calorimeter(HEIC) is currently being developed as a homogeneous calorimeter that utilizes long bismuth germanate(BGO) scintillation crystals as both absorbers and detectors. To accurately measure the energy deposition in the BGO bar of HEIC, a highdynamic-range readout method using a silicon photomultiplier(SiPM) and multiphotodiode(PD) with different active areas has been proposed. A prototype readout system that adopts multichannel charge measurement ASICs was also developed to read out the combined system of SiPMs and PDs. Preliminary tests confirmed the feasibility of the readout scheme, which is expected to have a dynamic range close to 10~6.

A 5.12-GHz LC-based phase-locked loop for silicon pixel readouts of high-energy physics

There is an urgent need for high-quality and high-frequency clock generators for high-energy physics experiments.The transmission data rate exceeds 10 Gbps for a single channel in future readout electronics of silicon pixel detectors.Others,such as time measurement detectors,require a high time resolution based on the time-to-digital readout architecture.A phase-locked loop(PLL)is an essential and broadly used circuit in these applications.This study presents an application-specific integrated circuit of a low-jitter,low-power LC-tank that is PLL fabricated using 55-nm CMOS technology.It includes a 3rd-order frequency synthesis loop with a programmable bandwidth,a divide-by-2 pre-scaler,standard low-voltage differential signaling interfaces,and a current mode logic(CML)driver for clock transmissions.All the d-flip-flop dividers and phase-frequency detectors are protected from single-event upsets using the triple modular redundancy technique.The proposed VCO uses low-pass filters to suppress the noise from bias circuits.The tested LC-PLL covers a frequency locking range between 4.74 GHz and 5.92 GHz with two sub-bands.The jitter measurements of the frequency-halved clock(2.56 GHz)are less than 460 fs and 0.8 ps for the random and deterministic jitters,respectively,and a total of 7.5 ps peak-to-peak with a bit error rate of 10^(-12).The random and total jitter values for frequencies of 426 MHz and 20 MHz are less than 1.8 ps and 65 ps,respectively.The LC-PLL consumed 27 mW for the core and 73.8 mW in total.The measured results nearly coincided with the simulations and validated the analyses and tests.

Design of fast adaptive readout system for wire scanners

A new wide-range fast readout system capable of adaptive identification is designed for wire scanners,which are used to measure beam profiles and emittance.This system is capable of handling varying current signals with Gaussian distributions and current pulses up to 1000 counts/s, as well as an input current range of 1 n A–1 m A. When tested, the resolution was found to exceed 3.68% for full scale, the nonlinearity was found to be less than 0.11%, and the measurement sensibility was found to be less than 5 p A. We believe that the system will play a crucial role in improving the measurement accuracy of beam diagnosis and the efficiency of accelerator operation,as well as decreasing the time required for beam tuning.This system was applied to the beam diagnosis of an injector II prototype for an accelerator-driven subcritical system and produced excellent measurement results. A description of the adaptive fast readout system for wire scanners is presented in this paper.

Readout electronics for CSR-ETF silicon strip array detector system

A readout electronics has been developed for the silicon strip array detector system of HIRFL-CSR-ETF.It consists of 48 front end electronics(FEE)boards,12 PXI-DAQ boards and one trigger board.It can implement energy and time measurements of 4608 channels.Each FEE board is based on 6 ASICs(ATHED),which implements energy and time measurements of 96 channels.The PXI-DAQ board meets requirements of high-speed counting and amount of readout channels and can process signals of 4 FEEs.The trigger board is developed to select the valid events.The energy linearity of the readout electronics is better than 0.3%in the dynamic range of 0.1-0.7V.In the test with a standard triple alpha source,the energy resolution was 1.8%at 5.48 MeV.This readout electronics enables the silicon strip array system to identify particles of A<14.

高速数字化三维集成式CCD-CMOS图像传感器

为了解决CCD与CMOS工艺兼容性低、互连集成制作难度大,以及芯片间接口匹配和高性能兼备等问题,对CCD器件拓扑结构与像元、CMOS读出电路、三维异质互连集成及高密度引脚封装等技术进行研究,提出了一种1024×256阵列规模的集成式CCD-CMOS图像传感器。该器件实现了CCD信号的高精度数字化处理、高速输出及多芯粒的技术融合,填补了国内CCDCMOS三维集成技术空白。测试结果表明:集成CCD-CMOS器件的光响应和成像功能正常,双边成像效果良好,图像无黑条和坏列,互连连通率(99.9%)满足三维集成要求,实现了集成式探测器件的大满阱高灵敏度成像(满阱电子数达165.28ke^(-)、峰值量子效率达86.1%)、高精度数字化(12bit)和高速输出(行频率达100.85kHz),满足集成化、数字化、小型化的多光谱探测成像系统要求。

基于磁性传感器的低失调温度补偿接口电路设计

面向磁性传感器在物联网(IoT)技术中的广泛应用,该文基于180 nm CMOS工艺设计了一种具有低失调电压,低温度漂移特性的霍尔传感器接口电路。针对霍尔传感器灵敏度的温度漂移特性,该文设计了一种感温电路并与查表法相结合,调节可编程增益放大器(PGA)的增益有效地降低了霍尔传感器的温度系数(TC)。在此基础上,通过在信号主通路中使用相关双采样(CDS)技术,极大程度上消除了霍尔传感器的失调电压。仿真结果表明,在–40°C~125°C温度范围内,霍尔传感器的TC从966.4 ppm/°C减小到了58.1 ppm/°C。信号主通路的流片结果表明,霍尔传感器的失调电压从25 mV左右减小到了4 mV左右,霍尔传感器的非线性误差为0.50%。芯片的总面积为0.69 mm^(2)。

一种集成图像处理功能的数字像元焦平面读出电路

设计了一种像元级数字化焦平面读出电路,克服了传统模拟读出电路技术的电荷容量局限,实现了更大的动态范围和更低噪声的数字化图像读出;同时在像元内部进行数字化图像处理,可实现非均匀校正(NUC)、盲元补偿、数字时间延迟积分(TDI)、空间滤波等图像预处理功能。该电路采用40 nm CMOS工艺流片,面阵规格为640×512,像元步进为30μm,全芯片尺寸约22 mm×19 mm。测试结果显示,该电路通过TDI、空间滤波功能可大幅降低(分别约90%和63%)输出图像空间噪声,提升成像质量。

超高灵敏度红外探测器测试评价

噪声等效温差(Noise Equivalent Temperature Difference,NETD)是评价红外探测器灵敏度的关键指标。通过改变读出电路结构,提高读出电路的电荷处理能力,使探测器的NETD值从10 mK量级提升至1 mK以下。当噪声小于1个灰度时,采用现有测试方法得到的NETD值较低,导致整机应用时识别距离评估过高,与实际结果不符。本文提出的优化方法使测试结果与系统应用指标更符合。经分析认为,所用探测器更适用于低速目标或者相对静止场景;与常规探测器相比,该探测器的识别距离受相同光学温度变化的影响更大。建议用户关注光学温度稳定性的影响。

基于带隙基准的改进型像元共享CTIA红外读出电路设计

为了提高红外读出电路动态范围、增强红外成像质量,加入暗电流抑制模块电路,设计了一种四像元分时共享的电容反馈跨阻放大器(CTIA)和带隙基准源相互配合的高性能红外读出电路。通过带隙基准源产生两个基准电压586 mV和293 mV,其中293 mV基准电压值的温漂系数达到1.49×10-6/℃,可对分流管的栅极和源极提供稳定的电压偏置,实现对暗电流的精准撇除。结果表明,该电路可实现电流信号从10 pA~10 nA宽动态范围的积分电压读出,读出数据通过线性拟合,拟合优度R 2达到0.9992,说明电路性能良好。此研究未来可应用到线列和面阵的红外探测器中。