We give the brief review on the related definition of the geometric phase independent of specific physical system based on the displacement opreator and the sqeezed operator, then show how the displacement operator an...We give the brief review on the related definition of the geometric phase independent of specific physical system based on the displacement opreator and the sqeezed operator, then show how the displacement operator and the squeezed operator can induce the general geometric phase. By means of the displacement operator and the squeezed operator concerning the circuit cavity mode state along a closed path in the phase space, we discuss specifically how to implement a two-qubit geometric phase gate in circuit quantum electrodynamics with both single photon interaction and two-photon interaction between the superconducting qubits and the circuit cavity modes. The experimental feasibility is discussed in detail.展开更多
First the research is conducted on the design of the two-phase sinusoidal power clock gen- erator in this paper. Then the design of the new adiabatic logic circuit adopting the two-phase sinusoidal power clocks—Clock...First the research is conducted on the design of the two-phase sinusoidal power clock gen- erator in this paper. Then the design of the new adiabatic logic circuit adopting the two-phase sinusoidal power clocks—Clocked Transmission Gate Adiabatic Logic (CTGAL) circuit is presented. This circuit makes use of the clocked transmission gates to sample the input signals, then the output loads are charged and discharged in a fully adiabatic manner by using bootstrapped N-Channel Metal Oxide Semiconductor (NMOS) and Complementary Metal Oxide Semiconductor (CMOS) latch structure. Finally, with the parameters of Taiwan Semiconductor Manufacturing Company (TSMC) 0.25μm CMOS device, the transient energy consumption of CTGAL, Bootstrap Charge-Recovery Logic (BCRL) and Pass-transistor Adiabatic Logic (PAL) including their clock generators is simulated. The simula-tion result indicates that CTGAL circuit has the characteristic of remarkably low energy consumption.展开更多
Since in designing the full adder circuits, full adders have been generally taken into account, so as in this paper it has been attempted to represent a full adder cell with a significant efficiency of power, speed an...Since in designing the full adder circuits, full adders have been generally taken into account, so as in this paper it has been attempted to represent a full adder cell with a significant efficiency of power, speed and leakage current levels. For this objective, a comparison between five full adder circuits has been provided. Applying floating gate technology and refresh circuits in the full adder cell lead to the reduction of leakage current on the gate node. The simulations were accomplished in this paper, through HSPICE software and 65 nm CMOS technology. The simulation results indicate the considerable efficiency of power consumption, speed and leakage current in the full adder cell rather than other cells.展开更多
We propose a theoretical scheme for realizing the general conditional phase shift gate of charge qubitssituated in a high-Q superconducting transmission line resonator.The phase shifting angle can be tuned from 0 to 2...We propose a theoretical scheme for realizing the general conditional phase shift gate of charge qubitssituated in a high-Q superconducting transmission line resonator.The phase shifting angle can be tuned from 0 to 2n bysimply adjusting the qubit-resonator detuning and the interaction time.Based on this gate proposal,we give a detailedprocedure to implement the three-qubit quantum Fourier transform with circuit quantum electrodynamics (QED).Acareful analysis of the decoherence sources shows that the algorithm can be achieved with a high fidelity using currentcircuit QED techniques.展开更多
The paper reveals the relation between the linear AND-OR gate and the emitter function logic. With theoretic calculation and PSPICE simulation, the paper proves that the linear AND-OR gates can work at super-high-spee...The paper reveals the relation between the linear AND-OR gate and the emitter function logic. With theoretic calculation and PSPICE simulation, the paper proves that the linear AND-OR gates can work at super-high-speed and can be multi-cascaded. On the basis of analyzing the high-speed switch units which coordinate with linear AND-OR gates, two kinds of emitter coupled logic circuits are designed. The paper also discusses the design principles of super-high-speed digital circuits, and some examples of combinational and sequential circuits using linear AND-OR gate are given.展开更多
基金Supported by the National Science Foundation of China under Grant Nos. 11074070, 10774042, and 10774163the Nature Science Foundation of Hunan Province under Grant No. 09JJ3121+1 种基金the Key Project of Science and Technology of Hunan Province under Grant Nos. 2010FJ2005 and 2008FJ4217the NKBRSFC under Grant No. 2010CB922904
文摘We give the brief review on the related definition of the geometric phase independent of specific physical system based on the displacement opreator and the sqeezed operator, then show how the displacement operator and the squeezed operator can induce the general geometric phase. By means of the displacement operator and the squeezed operator concerning the circuit cavity mode state along a closed path in the phase space, we discuss specifically how to implement a two-qubit geometric phase gate in circuit quantum electrodynamics with both single photon interaction and two-photon interaction between the superconducting qubits and the circuit cavity modes. The experimental feasibility is discussed in detail.
基金Supported by the National Natural Science Foundation of China (No. 60273093)the Natural Science Foundation of Zhejinag Province(No. Y104135) the Student Sci-entific Research Foundation of Ningbo university (No.C38).
文摘First the research is conducted on the design of the two-phase sinusoidal power clock gen- erator in this paper. Then the design of the new adiabatic logic circuit adopting the two-phase sinusoidal power clocks—Clocked Transmission Gate Adiabatic Logic (CTGAL) circuit is presented. This circuit makes use of the clocked transmission gates to sample the input signals, then the output loads are charged and discharged in a fully adiabatic manner by using bootstrapped N-Channel Metal Oxide Semiconductor (NMOS) and Complementary Metal Oxide Semiconductor (CMOS) latch structure. Finally, with the parameters of Taiwan Semiconductor Manufacturing Company (TSMC) 0.25μm CMOS device, the transient energy consumption of CTGAL, Bootstrap Charge-Recovery Logic (BCRL) and Pass-transistor Adiabatic Logic (PAL) including their clock generators is simulated. The simula-tion result indicates that CTGAL circuit has the characteristic of remarkably low energy consumption.
文摘Since in designing the full adder circuits, full adders have been generally taken into account, so as in this paper it has been attempted to represent a full adder cell with a significant efficiency of power, speed and leakage current levels. For this objective, a comparison between five full adder circuits has been provided. Applying floating gate technology and refresh circuits in the full adder cell lead to the reduction of leakage current on the gate node. The simulations were accomplished in this paper, through HSPICE software and 65 nm CMOS technology. The simulation results indicate the considerable efficiency of power consumption, speed and leakage current in the full adder cell rather than other cells.
基金Supported by the Foundation for the Author of National Excellent Doctoral Dissertation of China under Grant No. 200524the Program for New Century Excellent Talents of China under Grant No. 06-0920
文摘We propose a theoretical scheme for realizing the general conditional phase shift gate of charge qubitssituated in a high-Q superconducting transmission line resonator.The phase shifting angle can be tuned from 0 to 2n bysimply adjusting the qubit-resonator detuning and the interaction time.Based on this gate proposal,we give a detailedprocedure to implement the three-qubit quantum Fourier transform with circuit quantum electrodynamics (QED).Acareful analysis of the decoherence sources shows that the algorithm can be achieved with a high fidelity using currentcircuit QED techniques.
基金Supported by the National Natural Science Foundation of China
文摘The paper reveals the relation between the linear AND-OR gate and the emitter function logic. With theoretic calculation and PSPICE simulation, the paper proves that the linear AND-OR gates can work at super-high-speed and can be multi-cascaded. On the basis of analyzing the high-speed switch units which coordinate with linear AND-OR gates, two kinds of emitter coupled logic circuits are designed. The paper also discusses the design principles of super-high-speed digital circuits, and some examples of combinational and sequential circuits using linear AND-OR gate are given.
