Gate Current for MOSFETs with High k Dielectric Materials

The MOSFET gate currents of high k gate dielectrics due to direct tunneling are investigated by using a new direct tunneling current model developed.The model includes both the inversion layer quantization effect with finite barrier height and the polysilicon depletion effect.The impacts of dielectric constant and conduction band offset as well as the band gap on the gate current are discussed.The results indicate that the gate dielectric materials with higher dielectric constant,larger conduction band offset and the larger band gap are necessary to reduce the gate current.The calculated results can be used as a guide to select the appropriate high k gate dielectric materials for MOSFETs.

Modeling of Gate Tunneling Current for Nanoscale MOSFETs with High-k Gate Stacks

A quantum model based on solutions to the Schrodinger-Poisson equations is developed to investigate the device behavior related togate tunneling current for nanoscale MOSFETs with high-k gate stacks. This model can model various MOS device structures with combinations of high-k dielectric materials and multilayer gate stacks,revealing quantum effects on the device performance. Comparisons are made for gate current behavior between nMOSFET and pMOSFET high- k gate stack structures. The results presented are consistent with experimental data, whereas a new finding for an optimum nitrogen content in HfSiON gate dielectric requires further experimental verifications.

Direct tunneling gate current model for symmetric double gate junctionless transistor with SiO_2/high-k gate stacked dielectric

A junctionless transistor is emerging as a most promising device for the future technology in the decananometer regime. To explore and exploit the behavior completely, the understanding of gate tunneling current is of great importance. In this paper we have explored the gate tunneling current of a double gate junctionless transistor（DGJLT） for the first time through an analytical model, to meet the future requirement of expected high-k gate dielectric material that could replace SiO2. We therefore present the high-k gate stacked architecture of the DGJLT to minimize the gate tunneling current. This paper also demonstrates the impact of conduction band offset,workfunction difference and k-values on the tunneling current of the DGJLT.

Activin A maintains cerebral cortex neuronal survival and increases voltage-gated Na^+ neuronal current

Activin A, which was first described in 1986, has been shown to maintain hippocampal neuronal survival. Activin A increases intracellular free Ca2＋ via L-type Ca2＋ channels. Our previous study showed that activin A promotes neurite growth of dorsal root ganglia in embryonic chickens and inhibits nitric oxide secretion. The present study demonstrated for the first time that activin A could maintain cerebral cortex neuronal survival in vitro for a long period, and that activin A was shown to increase voltage-gated Na＋ current （/Na） in Neuro-2a cells, which was recorded by patch clamp technique. The present study revealed a novel mechanism for activin A, as well as the influence of activin A on neurons by regulating expressions of vasoactive intestine peptide and inducible nitric oxide synthase.

Gate current modeling and optimal design of nanoscale non-overlapped gate to source/drain MOSFET

A novel nanoscale MOSFET with a source/drain-to-gate non-overlapped and high-k spacer structure has been demonstrated to reduce the gate leakage current for the first time.The gate leakage behaviour of the novel MOSFET structure has been investigated with the help of a compact analytical model and Sentaurus simulation. A fringing gate electric field through the dielectric spacer induces an inversion layer in the non-overlap region to act as an extended S/D（source/drain） region.It is found that an optimal source/drain-to-gate non-overlapped and high-A：spacer structure has reduced the gate leakage current to a great extent as compared to those of an overlapped structure.Further,the proposed structure had improved off current,subthreshold slope and drain induced barrier lowering（DIBL） characteristics.It is concluded that this structure solves the problem of high leakage current without introducing extra series resistance.

Modified model of gate leakage currents in AlGaN/GaN HEMTs

It has been reported that the gate leakage currents are described by the Frenkel-Poole emission(FPE) model,at temperatures higher than 250 K.However,the gate leakage currents of our passivated devices do not accord with the FPE model.Therefore,a modified FPE model is developed in which an additional leakage current,besides the gate(ⅠⅡ),is added.Based on the samples with different passivations,the ⅠⅡcaused by a large number of surface traps is separated from total gate currents,and is found to be linear with respect to(φB-Vg)0.5.Compared with these from the FPE model,the calculated results from the modified model agree well with the Ig-Vgmeasurements at temperatures ranging from 295 K to 475 K.

Effect of SiN:H_x passivation layer on the reverse gate leakage current in GaN HEMTs

This paper concentrates on the impact of SiN passivation layer deposited by plasma-enhanced chemical vapor deposition（PECVD） on the Schottky characteristics in GaN high electron mobility transistors（HEMTs）. Three types of SiN layers with different deposition conditions were deposited on GaN HEMTs. Atomic force microscope（AFM）, capacitance-voltage（C-V）, and Fourier transform infrared（FTIR） measurement were used to analyze the surface morphology, the electrical characterization, and the chemical bonding of SiN thin films, respectively. The better surface morphology was achieved from the device with lower gate leakage current. The fixed positive charge Qf was extracted from C-V curves of Al/SiN/Si structures and quite different density of trap states（in the order of magnitude of 1011-1012 cm^（-2）） was observed.It was found that the least trap states were in accordance with the lowest gate leakage current. Furthermore, the chemical bonds and the %H in Si-H and N-H were figured from FTIR measurement, demonstrating an increase in the density of Qf with the increasing %H in N-H. It reveals that the effect of SiN passivation can be improved in GaN-based HEMTs by modulating %H in Si-H and N-H, thus achieving a better Schottky characteristics.

FORWARD GATED-DIODE R-G CURRENT METHOD: A SIMPLE NOVEL TECHNIQUE FOR CHARACTERIZING LATERAL LIGHTLY DOPING REGION OF LDD MOSFET's

This paper presents a simple novel technique-forward gated-diode R-G current method-to determine the lateral lightly-doped source/drain (S/D) region interface state density and effective surface doping concentration of the lightly-doped drain (LDD) N- MOSFET's simultaneously. One interesting result of the numerical analysis is the direct characterization of the interface state density and characteristic gate voltage values corresponding to LDD effective surface doping concentration. It is observed that the S/D N- surface doping concentration and corresponding region's interface state density are R-G current peak position and amplitude dependent, respectively. It is convincible that the proposed method is well suitable for the characterization of deep sub-micron MOSFET's in the current ULSI technology.

Subthreshold current model of fully depleted dual material gate SOI MOSFET

Dual material gate SOI MOSFET with asymmetrical halo can suppress short channel effect and increase carriers transport efficiency. The analytical model of its subthreshold drain current is derived based on the explicit solution of two-dimensional Poisson’s equation in the depletion region. The model takes into consideration the channel length modulation effect and the contribution of the back channel current component. Its validation is verified by comparision with two dimensional device simulator MEDICI.

Optimization of ambipolar current and analog/RF performance for T-shaped tunnel field-effect transistor with gate dielectric spacer

A new T-shaped tunnel field-effect transistor(TTFET) with gate dielectric spacer(GDS) structure is proposed in this paper. To further studied the effects of GDS structure on the TTFET, detailed device characteristics such as current-voltage relationships, energy band diagrams, band-to-band tunneling(BTBT) rate and the magnitude of the electric field are investigated by using TCAD simulation. It is found that compared with conventional TTFET and TTFET with gate-drain overlap(GDO) structure, GDS-TTFET not only has the minimum ambipolar current but also can suppress the ambipolar current under a more extensive bias range. Furthermore, the analog/RF performances of GDS-TTFET are also investigated in terms of transconductance, gate-source capacitance, gate-drain capacitance, cutoff frequency, and gain bandwidth production. By inserting a low-κ spacer layer between the gate electrode and the gate dielectric, the GDS structure can effectively reduce parasitic capacitances between the gate and the source/drain, which leads to better performance in term of cutoff frequency and gain bandwidth production. Finally, the thickness of the gate dielectric spacer is optimized for better ambipolar current suppression and improved analog/RF performance.

Two-dimensional models of threshold voltage and subthreshold current for symmetrical double-material double-gate strained Si MOSFETs

The two-dimensional models for symmetrical double-material double-gate （DM-DG） strained Si （s-Si） metal-oxide semiconductor field effect transistors （MOSFETs） are presented. The surface potential and the surface electric field ex- pressions have been obtained by solving Poisson＇s equation. The models of threshold voltage and subthreshold current are obtained based on the surface potential expression. The surface potential and the surface electric field are compared with those of single-material double-gate （SM-DG） MOSFETs. The effects of different device parameters on the threshold voltage and the subthreshold current are demonstrated. The analytical models give deep insight into the device parameters design. The analytical results obtained from the proposed models show good matching with the simulation results using DESSIS.

Stress-induced leakage current characteristics of PMOS fabricated by a new multi-deposition multi-annealing technique with full gate last process

In the process of high-k films fabrication, a novel multi deposition multi annealing （MDMA） technique is introduced to replace simple post deposition annealing. The leakage current decreases with the increase of the post deposition annealing （PDA） times. The equivalent oxide thickness （EOT） decreases when the annealing time（s） change from 1 to 2. Furthermore, the characteristics of SILC （stress-induced leakage current） for an ultra-thin SiO2/HfO2 gate dielectric stack are studied systematically. The increase of the PDA time（s） from 1 to 2 can decrease the defect and defect generation rate in the HK layer. However, increasing the PDA times to 4 and 7 may introduce too much oxygen, therefore the type of oxygen vacancy changes.

基于载流子抽取模型的Trench Gate/Field-stop IGBT驱动器有源箝位功能分析

针对Trench gate/Field-stop IGBT结构特有的关断过程中集电极电流下降率不可控问题,引入了载流子抽取模型来模拟器件关断过程中的集电极电流下降阶段器件内部载流子的动态行为特性,并以此为基础分析了驱动器为适应Trench gate/Field-Stop IGBT结构这种关断特性而引入的有源箝位功能的作用机理,验证了载流子抽取模型在器件级与电路级交互作用分析中的实用性,为后续实现器件与电路的最佳匹配奠定了基础。

The electrical characteristics of a 4H-silicon carbide metal-insulator-semiconductor structure with Al_2O_3 as the gate dielectric

A 4H-silicon carbide metal-insulator-semiconductor structure with ultra-thin Al2O3 as the gate dielectric, deposited by atomic layer deposition on tile epitaxial layer of a 4H-SiC （0001） 80N-/N＋ substrate, has been fabricated. The experimental results indicate that the prepared ultra-thin Al2O3 gate dielectric exhibits good physical and electrical characteristics, including a high breakdown electrical field of 25 MV/cm, excellent interface properties （1 × 10^14 cm^-2） and low gate-leakage current （IG = 1 × 10^-3 A/cm 2@Eox = 8 MV/cm）. Analysis of the current conduction mecha- nism on the deposited Al2O3 gate dielectric was also systematically performed. The confirmed conduction mechanisms consisted of Fowler-Nordheim （FN） tuaneling, the Frenkel-Poole mechanism, direct tunneling and Schottky emission, and the dominant current conduction mechanism depends on the applied electrical field. When the gate leakage current mechanism is dominated by FN tunneling, the barrier height of SiC/Al2O3 is 1.4 eV, which can meet the requirements of silicon carbide metal-insulator-semiconductor transistor devices.

Characteristics of high-quality HfSiON gate dielectric prepared by physical vapour deposition

This paper presents a method using simple physical vapour deposition to form high-quality hafnium silicon oxynitride （HfSiON） on ultrathin SiO2 buffer layer. The gate dielectric with 10A （1A = 0.1 nm） equivalent oxide thickness is obtained. The experimental results indicate that the prepared HfSiON gate dielectric exhibits good physical and electrical characteristics, including very good thermal stability up to 1000℃, excellent interface properties, high dielectric constant （k = 14） and low gate-leakage current （Ig = 1.9 × 10^-3 A/cm^2@Vg = Vfb - 1 V for EOT of 10 A）. TaN metal gate electrode is integrated with the HfSiON gate dielectric.The effective work function of TaN on HfSiON is 4.3 eV, meeting the requirements of NMOS for the metal gate. And, the impacts of sputtering ambient and annealing temperature on the electrical properties of HfSiON gate dielectric are investigated.

High performance trench MOS barrier Schottky diode with high-k gate oxide

A novel trench MOS barrier Schottky diode（TMBS） device with a high-k material introduced into the gate insulator is reported, which is named high-k TMBS. By simulation with Medici, it is found that the high-k TMBS can have 19.8% lower leakage current while maintaining the same breakdown voltage and forward turn-on voltage compared with the conventional regular trench TMBS.

Insulated gate bipolar transistor inverter for arc welding

This paper introduces the Insulated gate bipolar transistor(IGBT)in- verter for arc welding.The principle of the inverter,the structure and charac- teristics of IGBT and the current feedback system using LEM current transduc- er are discussed.By the measurement of its efficiency and power factor and the tests of welding processes,the developed 150A IGBT inverter proves to be a kind of energy-saving portable power supply for arc welding with broad prospects.

The leakage current mechanisms in the Schottky diode with a thin Al layer insertion between Al_(0.245)Ga_(0.755)N/GaN heterostructure and Ni/Au Schottky contact

This paper investigates the behaviour of the reverse-bias leakage current of the Schottky diode with a thin Al inserting layer inserted between Al0.245Ga0.755N/GaN heterostructure and Ni/Au Schottky contact in the temperature range of 25 350℃. It compares with the Schottky diode without Aluminium inserting layer. The experimental results show that in the Schottky diode with Al layer the minimum point of I-V curve drifts to the minus voltage, and with the increase of temperature increasing, the minimum point of I V curve returns the 0 point. The temperature dependence of gate-leakage currents in the novelty diode and the traditional diode are studied. The results show that the Al inserting layer introduces interface states between metal and Al0.245Ga0.755N. Aluminium reacted with oxygen formed Al2O3 insulator layer which suppresses the trap tunnelling current and the trend of thermionic field emission current. The reliability of the diode at the high temperature is improved by inserting a thin Al layer.

A 16-channel gated integrator for high-resolution energy spectroscopy systems

A 16-channel gated integrator(GI) module following semi-Gaussian shaping amplifiers was developed for high-resolution energy spectroscopy systems at Institute of Modern Physics,Chinese Academy of Sciences.This GI solved the ballistic deficit problem by integrating the signal until all the charge was collected from the detector at counting rates up to 100 K.In this paper,a fast shaper was used to optimize the gate logic to ensure nonlinearity of the GI less than 0.17%;and a novel compensation approach,to reduce the charge injection from the switches in the GI; and a T-switch configuration,to eliminate leakage current in the reset switch.